Printed-wiring board

Details Printed-wiring board Printed-wiring board

2000-11-01

2002-12-03

Paladini, Albert W. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S255000, C174S261000, C361S777000, C361S792000, C361S803000

Reexamination Certificate

active

06489574

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed-wiring board. More particularly, the invention relates to a printed-wiring board provided at least with a first layer and a second layer, having multi-terminal devices, such as a grid array package ICs, installed hereon with a plurality of terminals arranged in a plane configuration.
2. Related Background Art
Conventionally, along with the electronic equipment the functions of which are made higher increasingly, the integration of semiconductor devices has been higher still, and the numbers of outer terminals of an LSI package are on the increase accordingly. There are in practical use, among some others, a ball grid array package (BGA) having 500 or more connecting terminals formed therefor, and a chip scale package (CSP) having connecting terminals arranged in the form of array at narrower pitches. For such package of grid array type, soldered bumps or some other terminals are formed in general on the bottom face of a package base plate. Then, electrical connections are implemented by assembling and connecting these terminals with the lands of a printed-wiring board.
Now, however, it is difficult to draw out pattern from the inner lands among many numbers of lands on a printed-wiring board with which are connected many numbers of terminals arranged for a package of grid array type. To counteract this, it has been practiced to provide a plurality of signal layers for the printed-wiring board of multi-layered structure or to effectuate the interruption of signal layers into the power supply-source layer and the ground layer.
In other words, if a package is of quad-flat package (QFP) or of tape carrier package (TPC), only one line of terminals is arranged on the outer side of a package so that signal lines can be drawn out from the terminals of the printed-wiring board easily without any particular arrangement. Therefore, it is good enough for a printed-wiring board to use just one layer as the signal layer. Thus, the other layers can be used for the power supply-source pattern, the ground patterns, and the like. However, for a printed-wiring board having a grid array type package assembled thereon, plural signal layers are needed in order to draw out signal lines from the inner lands. The resultant number of layers becomes many for the printed-wiring board in use or the signal lines should be interrupted into the power supply-source layer and ground layer in order to suppress the layer numbers of the printed-wiring board.
Here, on the other hand, there is a constant demand in making the clock frequency of digital circuit of electronic equipment higher still.
Now, hereunder, the existing problems will be described, at first, as to a package of grid array type assembled on a printed-wiring board.
FIG. 15
is a plan view which shows the first layer, the surface, of the conventional double-layer printed wiring board generally in use, on which a ball grid array package is assembled.
FIG. 16
is a plan view which shows the second layer, the reverse side, of the printed wiring board represented in
FIG. 15
, and arranged to be a perspective view in order to make the positional relations clear between them. Then, in order to distinguish the positional relations with lands in
FIG. 15
, the land positions are indicated by dotted lines in FIG.
16
.
In
FIG. 15
, signal lines
52
and
62
, and the power supply-source pattern
54
and ground pattern
56
are connected with the land
51
. Of many lands, it is not easy to draw out patterns from the inner ones. Thus, the inner lands are connected with signal pattern on the second layer shown in
FIG. 16
by way of through holes
53
,
55
, and
57
.
In
FIG. 16
, a part of signal pattern shown in
FIG. 16
is connected with the signal pattern on the second layer by way of through holes. For example, the signal line
62
is connected with the signal line
58
on the second layer by way of a through hole
53
. Likewise, the power supply-source pattern
54
is connected with the power supply-source pattern
59
on the second layer by way of a through hole
55
. The ground pattern
56
is connected with the ground pattern
60
on the second layer by way of a through hole
57
. Here, a reference numeral
61
designates the by-pass capacitor land which is assembled between the power supply-source pattern
63
and the ground pattern
64
.
As clear from
FIG. 16
, the grid array package assembled on a double-layer printed wiring board makes it impossible to arrange the ground pattern freely due to the existence of signal lines and others. The ground pattern should be made far from being in an ideal plane configuration. The structure of the ground pattern tends to become such a portion that may present many chipping.
To avoid this condition, a multi-layer printed wiring board is used, in which signal layers are increased so that a layer is dedicated for use of the power supply-source, and another for grounding. In this case, however, costs become significantly high, and also, there is a problem encountered that printed wiring board becomes heavier.
Now, the description will be made of the problems existing in using a printed wiring board having digital circuits installed thereon for the use of a high speed clocking frequency.
Generally, when considering a differential mode irradiation, the field strength in the direction of maximum irradiation can be expressed by the following formula (“A Practical Technique for Gradually Decreasing Noises” p.324, Published by Jatech Shuppan):
E=
263×10
−16
(
f
2·
A·I
) (1
/r
)
where E is field strength (V/m); f, frequency (Hz); A, loop area (m
2
), I, current (A), and r, distance (m) to receiving antenna.
As understandable from the above formula, it is desirable to make the loop area A as small as possible for the high frequency current I which may create the problem of irradiated noises. In other words, in order to prevent noises from being irradiated, the digital signal lines should be made as short as possible, and also, the ground pattern or the power supply-source pattern where return current runs should desirably be arranged as near the signal lines as possible. Also, among digital circuits, special care should be given to the clock signal lines through which high frequency signals flow. Likewise, it is desirable to make the loop area A as small as possible for a high frequency current which runs between the power supply-source and the ground.
Also, the ground pattern that has many chipped portions may result in the increase of reflection that tends to invite the disturbance of signal waveforms or may invite ground bounces. Then, it becomes easier for equipment to malfunction.
Now, with reference to
FIG. 17
, this condition will be described further in detail.
FIG. 17
is a cross-sectional view of a printed wiring board which schematically shows the relationship between the pattern arrangement of signal lines, power supply-source lines, ground lines, and others on the printed wiring board, and the loop areas.
In
FIG. 17
, a reference numeral
101
designates an IC output buffer;
102
, an IC that receives signals;
103
, a signal line;
105
, a power supply-source line;
106
, a ground line; and
104
, a bypass capacitor.
The loop area A expressed in the above formula corresponds to the loop A surrounded by the signal line
103
and the ground line
106
in
FIG. 17
, the loops B and C surrounded by the power supply-source line
105
and ground line
106
up to the position where the bypass capacitor
104
is assembled, and the loops D and E which are created when the bypass capacitor does not work effectively.
FIG. 18
is a cross-sectional view of the printed wiring board which corresponds to
FIG. 17
, and shows the changes of the loop areas due to the chipping of the ground pattern.
In
FIG. 16
, there are chipping portions for the ground patterns
60
and
64
in the vicinity of the package assembling lands. With the signal output pins being considered as reference, for example, this i

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