Etching a substrate: processes – Nongaseous phase etching of substrate
Reexamination Certificate
2006-11-21
2006-11-21
Norton, Nadine (Department: 1765)
Etching a substrate: processes
Nongaseous phase etching of substrate
C257S773000, C438S381000, C438S778000, C438S793000, C438S794000, C438S791000
Reexamination Certificate
active
07138068
ABSTRACT:
A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.
REFERENCES:
patent: 5027253 (1991-06-01), Lauffer et al.
patent: 5261153 (1993-11-01), Lucas
patent: 5796587 (1998-08-01), Lauffer et al.
patent: 6005777 (1999-12-01), Bloom et al.
patent: 6183880 (2001-02-01), Yoshioka et al.
patent: 6346335 (2002-02-01), Chen et al.
patent: 6407929 (2002-06-01), Hale et al.
patent: 6541137 (2003-04-01), Kingon et al.
patent: 6660406 (2003-12-01), Yamamoto et al.
patent: 2003/0113443 (2003-06-01), Kingon et al.
patent: 2004/0256731 (2004-12-01), Mao et al.
patent: 2006/0002097 (2006-01-01), Borland et al.
Croswell Robert T.
Dunn Gregory J.
Magera Jaroslaw A.
Savic Jovica
Tungare Aroon V.
George Patricia A.
Motorola Inc.
Norton Nadine
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