Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-05-04
2001-07-31
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000, C361S768000, C361S772000, C361S777000, C361S783000, C257S738000, C257S778000, C257S779000, C257S786000
Reexamination Certificate
active
06268568
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to a printed circuit board (PCB) and a semiconductor package produced using the PCB and, more particularly, to a high density, high reliability ball grid array (BGA) semiconductor package having oval-shaped solder ball lands for increased resistance to shear forces caused by thermal expansion.
2. Description of the Related Art
As is well known to those skilled in the art, typical BGA semiconductor packages, BGA semiconductor packages using flexible printed circuit boards, and chip scale semiconductor packages are all surface-mounted types of semiconductor packages, each of which has a semiconductor chip bonded to the upper surface of a circuit board using a bonding agent. A plurality of solder balls are welded to lands on the lower surface of the circuit board and are used as input/output signal terminals of the package. Since the above semiconductor packages are capable of effecting a large number of signal input/output terminals in a relatively small area, they comport well with the recent trend of semiconductor packages that are small, compact, light and thin, and for that reason, are widely preferred and used.
The basic construction of the above packages is similar, so only the construction of a typical BGA semiconductor package will be described hereinbelow in conjunction with
FIGS. 1A and 1B
.
In a typical BGA package, a semiconductor chip
2
′ having an integrated circuit and a plurality of signal input/output pads
4
′ on a surface thereof is bonded to the central portion of the upper surface of a printed circuit board (PCB)
10
′ by a bonding layer
6
′. The PCB
10
′ comprises a resin substrate
11
′ having a circuit pattern on each of the upper and lower surfaces thereof. The circuit patterns on the upper and lower surfaces of the substrate
11
′ are formed by a plurality of conductive traces
12
′,
13
′, respectively. The conductive traces
12
′ and
13
′ are coated over with a high molecular resin solder mask
30
′, except at selected areas where it is desired to solder to them.
In more detail, a chip pad
16
′, which is a copper layer having a predetermined size, is formed on the central portion of the upper surface of the resin substrate
11
′ to receive and mount the chip
2
′. The chip
2
′ is bonded to the pad
16
′ by a bonding layer
6
′. A plurality of first conductive traces
12
′ are formed on the upper surface of the substrate
11
′ at positions spaced apart from the outside edge of the chip pad
16
′ and from each other at predetermined intervals, thereby forming an upper circuit pattern. The upper circuit pattern is coated with a solder mask
30
′. A plurality of second conductive traces
13
′ are formed on the lower surface of the substrate
11
′ and are each electrically connected to an associated one of the first conductive traces
12
′ through conductive via holes
14
′. A circular solder ball land
15
′, having a double-layered construction comprising a nickel layer
15
b
′ and a gold layer
15
c
′,is formed on each of the second conductive traces
13
′ through either an electrolytic plating process or an electroless plating process. A solder ball
20
′, made of an Sn/Pb alloy, is welded to each of the solder ball lands
15
′ and is used as a signal input/output terminal of the package
100
′ during signal communication of the package
100
′ with a main board m′ (see FIG.
1
D). The signal input/output pads
4
′ of the chip
2
′ are electrically connected to the first conductive traces
12
′ using an electrical connection means
40
′, such as a plurality of gold or aluminum wires or bumps, respectively. The semiconductor chip
2
′ and the electrical connection means
40
′ are encapsulated using a packaging material, such as epoxy molding compound or “glop top,” thereby forming an envelope
50
′ on one side of the package. The envelope
50
′ protects the chip
2
′ and the electrical connection means
40
′ from intrusion of harmful electrical, mechanical and chemical environmental elements.
The above BGA package
100
′ communicates signals with a main board. During such communication, a signal from the semiconductor chip
2
′ passes through the electric connection means
40
′, the resin substrate
11
′, the first conductive traces
12
′ on the upper surface of the substrate
11
′, the conductive via holes
14
′, the second conductive traces
13
′ on the lower surface of the substrate
11
′, the circular solder ball lands
15
′, and the solder balls
20
′, in that order, prior to being transmitted to the main board. When the package
100
′ is activated by electric power supplied from a power source, the chip
2
′ performs its intrinsic electrical functions.
However, a typical BGA package
100
′ having circular solder ball lands
15
′ is somewhat problematic in that the fatigue life of the solder balls
20
′ welded to the lands
15
′ is somewhat short for reasons discussed below, and this reduces the operational reliability of the package
100
′. In addition, the width of each neck point between the solder ball lands
15
′ is relatively narrow, thus limiting the number of second conductive traces
13
′ that can be formed within such neck points. This, in turn, limits the design flexibility of the BGA packages. Such problems are described in more detail hereinbelow in conjunction with
FIGS. 1B
to
1
D.
When the BGA package
100
′ is mounted on the surface of a main board m′ and in operation, the chip
2
′ typically generates heat. The amount of heat generated by the chip
2
′ typically increases in proportion to the clock frequency. The heat from the chip
2
′ is radially dissipated to the surroundings by the PCB
10
′ positioned under the chip
2
′, as shown in
FIGS. 1A and 1B
. The amount of heat transferred to the PCB
10
′ by the chip
2
′ is greatest at the portion of the PCB
10
′ closest to the outside edge of the chip
2
′, relative to portions more remote from the chip's edge, as shown schematically in the graph of FIG.
1
C. In
FIG. 1C
, the central perpendicular axis of the graph corresponds to the outside edge of the chip
2
′.
When the temperatures of both the chip
2
′ and the PCB
10
′ increase as described above, the PCB
10
′ expands. However, since the solder balls
20
′ welded to the solder ball lands
15
′ of the package
100
′ are fixed on the main board m′, a shearing stress is applied to both the lands
15
′ and the solder balls
20
′ in a radial direction around the center of the chip
2
′.
This shearing stress in the lands
15
′ and the solder balls
20
′ is higher in those that are closer to the chip
2
′ than in those that are more remote from the chip
2
′ as shown in FIG.
1
D. In
FIG. 1D
, the level of the shearing stress a, b, c and d acting on the lands
15
′ and the solder balls
20
′ varies in accordance with the position of the lands
15
′ and the solder balls
20
′ relative to the chip
2
′, that is, a>b>c>d. When the shearing stress is too high for the lands
15
′ and the solder balls
20
′ to resist, they can fracture, and the fatigue life of the solder balls
20
′ is substantially reduced. The solder balls
20
′ will ultimately fracture, beginning with the solder balls
20
′ closest to the chip
2
′, and proceeding outward to the solder balls
20
′ furthest away from the chip
2
′. It should be noted that a BGA package
100
′ will typically fail to function totally when only one
Anam Semiconductor Inc.
Gaffin Jeffrey
Lawrence Don C.
Skjerven Morrill & MacPherson LLP
Vigushin John B.
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