Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Reexamination Certificate
2001-07-25
2003-06-24
Bradley, P. Austin (Department: 2833)
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
C439S108000, C439S055000, C439S083000, C439S092000, C174S051000, C361S803000, C361S799000
Reexamination Certificate
active
06582238
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of Japanese Patent Application No. 2000-243282 filed on Aug. 10, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed circuit board on which ICs are mounted, which is suitably used for electronics that are required to have a reduced noise level, such as an IC for controlling vehicle braking.
2. Description of the Related Art
Recently, various regulations have required a reduction in the noise level of ICs, a typical example of which is a central processing unit. In a conventional IC, two opposed pins (two terminals respectively disposed at opposed two sides when the IC forms a rectangle) receive a source potential and a ground potential, respectively. However, plural terminals are conventionally arranged for receiving the source potential and the ground potential in an IC, in view of noise regulations.
In such a case, because the number of required pins is increased, package size and the number of bypass-capacitors are increased. As a result, an area of a substrate occupied by the bypass-capacitors and wiring members for connecting them is increased.
Further, this effect lessens flexibility of substrate pattern design to make the noise countermeasures on the substrate difficult. As a result, the noise level may be raised on the contrary. Incidentally, it is conceivable that a multilayered substrate can solve the above-described problem; however, the multilayered substrate results in high cost.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problem. An object of the present invention is to decrease a noise level while suppressing an increase in occupied substrate area.
According to the present invention, in a printed circuit board on which a plurality of pins are arranged to form a generally polygonal shape, the pins includes a first pin as a ground terminal and a second pin as a source terminal. The ground terminal is disposed at a corner portion of the generally polygonal shape, and the source terminal adjoins the ground terminal. Further, a first conductive region extends radially from the corner portion of the polygonal shape and is electrically connected to the ground terminal.
Because the source terminal adjoins the ground terminal, a substrate area occupied by a bypass capacitor can be restricted from increasing. Further, because the ground terminal is electrically connected to the first conductive region, ground impedance can be lowered, resulting in noise reduction.
REFERENCES:
patent: 4880386 (1989-11-01), Grabbe et al.
patent: 5131852 (1992-07-01), Grabbe et al.
patent: 5490041 (1996-02-01), Furukawa et al.
patent: 5777853 (1998-07-01), Dorfmeyer
patent: A-10-223997 (1998-08-01), None
Kawata Hiroyuki
Kobayashi Kimio
Unou Takanori
Bradley P. Austin
Denso Corporation
Nguyen Truc
Posz & Bethards, PLC
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