Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-03-30
2001-09-04
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S767000, C029S840000
Reexamination Certificate
active
06284984
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a printed circuit board, on whose surface a ball grid array element is mounted.
DESCRIPTION OF THE PRIOR ART
A ball grid array (hereinafter abbreviated as BGA), a sort of semiconductor element, is a multi-terminal semiconductor element, on which many solder balls are formed on its bottom surface.
Mounting of this BGA on a printed circuit board is basically accomplished by melting solder balls by heating, and solidifying the solder balls onto conductor pads formed opposite to the solder balls on the printed circuit board, respectively.
However, the BGA and the printed circuit board are only connected by many solder balls and conductor pads having small size. Therefore mechanical stresses resulting from bending, vibration, impact and the like working on the printed circuit board after its mounting tend to invite poor contact between solder balls and conductor pads or peeling of conductor pads. Many mounting methods have already been devised to solve this technical problem.
One of these mounting methods is an under-fill method. In this method, liquid resin is injected between a BGA and the printed circuit board after the BGA is mounted as described above. Then the liquid resin is hardened to adhere the BGA to the printed circuit board in an integrated manner and thereby to increase the bonding strength.
For mounting a BGA on a printed circuit board configured by stacking a plurality of conductor layers, there has been a method disclosed in the Japanese Patent Laid-open No. Hei 9-246684 (disclosed on Sep. 19, 1997). This method will be described below as an example of the prior art.
FIG. 7
is a longitudinal sectional view of the BGA mounting structure of the prior art.
A circuit board
130
has of an opening
130
d
and pads
140
a
to
140
f.
The opening
130
d
has a stepwise structure increasing in depth toward the center, provided in the part where a BGA
110
is to be mounted. The pads
140
a
to
140
f
connected to patterns
130
e
to
130
j
in different exposed parts of a multi-layered circuit board
130
and to be mounted with solder balls
120
a
to
120
f.
The BGA
110
has the solder balls
120
a
to
120
f,
growing in size toward the center so as to be mounted on the pads
140
a
to
140
f
provided on the circuit board
130
. The solder balls
120
a
to
120
f
are melted on the pads
140
a
to
140
f
to connect the circuit board
130
and the BGA
110
.
However, the conventional under-fill method referred to above involves the extra steps of resin injection and hardening, resulting in the problems of slower production and higher manufacturing costs.
Furthermore, the injection resin, once hardened, is extremely difficult to remove, making it impossible to replace any BGA by itself whose contact has become poor and rendering the printed circuit substantially irreparable. Therefore many BGA-mounted printed circuit boards have to be discarded in whole, entailing extremely high repair costs.
The BGA mounting structure disclosed in the Japanese laid-open patent also involves the problem of inadequate mechanical connective strength between the BGA
100
and the circuit board
130
and poor electrical reliability of their connection. Because the solder balls
120
a
to
120
f
are only bonded to the pads
140
a
to
140
f,
each of a very small size, resulting in insufficient bonding strength and easy peeling of the pads
140
a
to
140
f.
Moreover, since the opening
130
d
can only be formed in a stepwise structure, there is the problem that the solder balls
120
a
to
120
f
cannot be electrically connected to the patterns
130
e
to
130
j
as desired, therefore strictly limiting the freedom of wiring and inhibiting sufficient enhancement of the wiring density.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a printed circuit board and a manufacturing method of a printed circuit board which ensure high mechanical bonding strength and reliable electrical connection and permit ready mounting.
A printed circuit board according to the present invention has: n (n: an integer) conducting pattern layers on each of which a wiring pattern is formed; (n+1) insulating patterns formed alternately with the conducting pattern layers; conducting pads formed on the wiring patterns of the conducting pattern layers; and openings continuous from the conducting pads to a surface of the topmost of the insulating layers, penetrating the insulating layers.
A manufacturing method of a printed circuit board according to the present invention has the steps of: forming alternately (n+1) (n: an integer) insulating patterns with n conducting pattern layers on each of which a wiring pattern is formed, and forming openings continuous from the surface of the topmost of the insulating layers to conducting pads formed on the wiring patterns of the conducting pattern layers.
According to the present invention, an internal conducting pattern layer not exposed on the surface and soldered parts of electronic parts are both mechanically bonded and electrically connected in a printed circuit board in which conducting pattern layers and insulating layers are alternately stacked. As the insulating layer that is located closer to the top surface than this conducting layer supports sideways of the soldered members of the electronic parts, the bonding strength of the electronic parts and the printed circuit board is enhanced.
REFERENCES:
patent: 4729061 (1988-03-01), Brown
patent: 5218761 (1993-06-01), Maniwa et al.
patent: 5263243 (1993-11-01), Taneda et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5543586 (1996-08-01), Crane, Jr. et al.
patent: 5744758 (1998-04-01), Takenouchi et al.
patent: 4-150095 (1992-05-01), None
patent: 7-79080 (1995-03-01), None
patent: 7-335992 (1995-12-01), None
patent: 9-246684 (1997-09-01), None
Japanese Office Action, dated Nov. 16, 1999, with English language translation of Japanese Eaminer's comments.
Gaffin Jeffrey
McGuireWoods LLP
NEC Infrontia Corporation
Norris Jeremy
LandOfFree
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