Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1998-12-30
2001-05-15
Gandhi, Jayprakash N. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S689000, C361S689000, C361S783000, C361S765000, C174S250000, C174S255000, C174S260000, C228S180210
Reexamination Certificate
active
06233157
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a printed circuit board, hereinafter “PCB” and a method for wiring signal lines on the same.
A plurality of semiconductor chips are mounted on a PCB and the PCB is mounted on a motherboard, thereby electrically connecting its pad to the motherboard.
When a chip select signal or an address signal is transmitted from the motherboard to the PCB, a corresponding semiconductor chip is selected or its address is designated. Accordingly, signal lines for transmitting a chip select signal and an address signal to each semiconductor chip are wired on the PCB. The signal lines vary as to what semiconductor chip is mounted on the PCB.
Namely, the signal lines vary as memory capacity of the semiconductor chip is 64M including 128M or 256M, and also vary as the type of semiconductor chip, e.g. an unstack type consisting of one chip by itself, or stack type consisting of a plurality of stacked chips.
First of all, four pads provided on the PCB are used as chip select signals, and each corresponding pad is connected to a chip select pin, typically a nineteenth pin (/cs). The four pads are named typically S
0
, S
1
, S
2
, and S
3
. Only two pads are used 4 chip selection in case that the semiconductor chip mounted on the PCB is the unstack type, and four pads are all used as chip selection in case that it is the stack type. The following Table 1 illustrates the fashion in particular.
TABLE 1
Pad No.
S0
S1
S2
S3
unstack chip
use
nonuse
use
nonuse
stack chip
use
use
use
use
As shown in Table 1, only pads S
0
and S
2
are used in the unstack type of the semiconductor chip, while four pads are all used in the stack type of that. Accordingly, in case of unstack type, the used pads S
0
and S
2
are connected to the nineteenth pin of the semiconductor chip via signal lines, and pads S
1
and S
3
are not connected to the nineteenth pin. On the other hand, in case of stack type, the four pads are all connected to the nineteenth pin of the semiconductor chip via signal lines. Thus, the wiring arrangement of signal lines varies as the semiconductor chip mounted on the PCB is the unstack type or the stack type.
In the meantime, the address signal is generally transmitted to a twentieth pin, a twenty-first pin and a thirty-sixth pin via pads on the PCB. The pins used for the address signal vary as the memory capacity of semiconductor chip is 64M or 128M on the one hand or 256 the other hand. The following Table 2 illustrates the fashion in particular.
TABLE 2
Pin No.
64M including 128M
256M
20
A13
A14
21
A12
A13
36
NC
A12
As shown in Table 2, in case that the memory capacitance of the semiconductor chip is 64M, the address signal is transmitted to the twentieth pin via the pad A
13
, to the twenty-first pin via the pad A
12
, while the thirty-sixth pin is not connected to any pad. The word NC means “No Connect”. In the meantime, in case of 256M, the address signal is transmitted to the twentieth pin via the pad A
14
, to the twenty-first pin via the pad A
13
and to the thirty-sixth pin via the pad A
12
. Accordingly, the wiring arrangement of signal lines varies as the memory capacity of chip is 64M or 256M.
As described above, the wiring arrangements of signal lines on the PCB vary with the semiconductor chips to be mounted. That is, there are totally four cases of different wiring arrangement of signal lines that the semiconductor chip is unstack/64M or 128M, unstack/256M, stack/64M 128M, and stack/256M.
Therefore, it is conventionally required to have four PCBs having different wiring arrangements according to the four cases. Particularly, the PCB is made pursuant to each wiring arrangement, therefore it incurs lots of time-consuming jobs for developing appropriate module, testing the PCB or mass-producing and delivering products to production line.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to solve the foregoing problems of conventional PCBs and to provide a method for wiring arrangement of signal lines and a PCB having convertibility with various types of semiconductor chip, e.g. unstack chip or stack chip and memory capacity of 64M or 256M without incurring additional design steps for wiring arrangement of signal lines.
So as to achieve the above object, the PCB in accordance with the present invention comprises as follows. Semiconductor chips having their peculiar functions are mounted on a PCB. Various signals from a motherboard where the PCB is mounted are selectively transmitted to each pin via outer pads of the PCB. A plurality of connecting lines are formed on the PCB for connecting the pins of the respective chips having same function each other. Each connecting line and its corresponding outer pad is connected via a plurality of signal lines so that each pin connected by the connecting lines is electrically connected to its corresponding outer pad. Connecting pads which are connectable electrically, are disposed at the plurality of signal lines or therebetween. The connecting pads are selectively connected via a jumper having resistance value of approximately 0(zero), depending on stacking or memory capacity of the semiconductor chip.
The wiring arrangement of signal lines will be described in detail according to peculiar function of pins on semiconductor chip.
An outer pad used in case that the semiconductor chip is unstack type, is connected to a chip select pin of one of two semiconductor chips disposed on both opposing sides of a PCB and is also connected to a no connect pin of the other semiconductor chip via a first signal line respectively.
Another pad used with the above pad in case that the semiconductor chip is stack type, is connected to a no connect pin of the semiconductor chip which of the chip select pin is connected to the above pad by the first signal line via a second signal line, and is also connected to a chip select pin of the semiconductor chip which of the no connect pin is connected to the above pad by the first signal line via a second signal line respectively.
A second connecting pad is disposed between the first and the second signal lines, and selectively connected by a first jump chip having resistance value of approximately 0 (zero), depending on the types of semiconductor chip, e.g. unstack/stack type. A first connecting pad is disposed at the second signal line and is connected by a second jump chip.
Furthermore, connecting lines are formed on the PCB so that the respective three pins of semiconductor chips transmitted an address signal from the motherboard are connected with pins of the same number. Seven connecting pads are disposed on the PCB and a second, a fourth and a seventh connecting pads among the seven are electrically connected to outer pads for transmitting the address signal. A first, a third and a sixth pads are connected to the connecting lines connecting the respective pins of a semiconductor chip via three signal lines. A fifth pad is connected to the signal line extended to the sixth pad via another connecting line. The respective connecting pads are selectively connected by jump chips, depending on the memory capacitance of semiconductor chip.
According to the above constitution of the present invention, there is no need to design wiring arrangement on the PCB, depending on the types of semiconductor chip, e.g. unstack/stack or memory capacity of 64M or 256M, since the corresponding connecting pads are selectively connected by jumpers.
Hereinafter, the best mode for carrying out the present invention will be described more fully below with reference to attached drawings.
REFERENCES:
patent: 5272664 (1993-12-01), Alexander et al.
patent: 5319602 (1994-06-01), Shishikura
patent: 5375084 (1994-12-01), Begun et al.
patent: 5512783 (1996-04-01), Wakefield et al.
patent: 5572457 (1996-11-01), Michael
patent: 5875136 (1999-02-01), Hsuan et al.
patent: 5936844 (1999-08-01), Walton
patent: 5941447 (1999-08-01), Chu et al.
patent: 5959937 (1999-09-01), Randolph et al.
patent: 1-225388 (1989-09-01), None
Lee Jung Woo
Suh Young Suk
Yoon Yong Sik
Foster David
Gandhi Jayprakash N.
Hyundai Electronics Industries Co,. Ltd.
Ladas & Parry
LandOfFree
Printed circuit board and method for wiring signal lines on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Printed circuit board and method for wiring signal lines on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Printed circuit board and method for wiring signal lines on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2485623