Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-02-09
2003-05-13
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C174S264000, C361S792000
Reexamination Certificate
active
06563057
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilayer printed circuit board and method for manufacturing such a printed circuit board, and more particularly to a method for forming a high-density conductive circuit onto a multilayer printed circuit board, to a structure of a contact hole for connecting an upper wiring layer with a lower wiring layer, and to a method for manufacturing same.
2. Background of the Invention
A method of manufacturing a printed circuit board in the prior art is described below, with reference make to FIG.
3
and FIG.
4
.
In a multilayer printed circuit board of the past, via holes are provided in an insulating board or insulating layer and a copper layer is formed on the outer surface of the insulating board or the insulating layer and inside the via holes, so as to make an electrical connection to a lower wiring layer.
The method of forming the printed circuit board wiring pattern can be divided into two general types. The first type, known as the subtractive method, is illustrated in cross-section form in FIG.
3
. First, as shown in FIG.
3
(
a
), a known method is used to manufacture a board
1
, which is fabricated as a fiberglass-based epoxy resin laminate and will serve as the core of the multilayer printed circuit board. In this board
1
, a hole
2
filled with resin and an internal layer circuit
3
are formed. Then, as shown in FIG.
3
(
b
), an insulation layer
4
having a thickness of 40 to 80 &mgr;m is formed onto the surface of the board
1
using, for example, the curtain coating method. Next, as shown in FIG.
3
(
c
), a photolithography process or CO
2
laser is used to form a via hole
5
having a diameter of 50 to 80 &mgr;m at required locations in the insulation layer
4
.
Next, as shown in FIG.
3
(
d
), an electrically conductive layer is formed on the surface of the insulation layer
4
by means of electroless copper plating, this electrical plating being done to a required thickness. Then, as shown in FIG.
3
(
e
), etching resist is formed, which is then used to perform etching of the copper to obtain a conductive circuit, as shown in FIG.
3
(
f
). Otherwise after an electrical conductive layer is formed, plating resist is formed in the negative image of the conductive circuit and electrical plating is done to the required thickness, after which the plating resist is peeled away, so as to form conductive circuits by means of quick-etching of the above-noted conductive layer. In this method, the pattern accuracy is determined by the resist resolution and the accuracy of the etching.
The second method is the additive method, which is illustrated in cross-section form in FIG.
4
. First, as shown in FIG.
4
(
a
), a known method is used to manufacture a board
1
, which is fabricated as a fiberglass-based epoxy resin laminate and will serve as the core of the multilayer printed circuit board. In this board
1
, a hole
2
filled with resin and an internal layer circuit
3
are formed. Then, as shown in FIG.
4
(
b
), an insulation layer
4
having a thickness of 40 to 80 &mgr;m is formed onto the surface of the board
1
using, for example, the curtain coating method. Next, as shown in FIG.
4
(
c
), a photolithography process or CO
2
laser is used to form a via hole
5
having a diameter of 50 to 80 &mgr;m at required locations in the insulation layer
4
.
Next, as shown in FIG.
4
(
d
) and FIG.
4
(
e
), an insulation material to which a catalyst has been added, is formed or a catalyst is added to the surface of the insulation layer
4
and the surface of non-conductive pattern part is covered with a plating resist, after which, as shown in FIG.
4
(
f
), selective copper plating is done so as to form the conductive pattern.
In the additive method, because the etching process step is not necessary and the pattern accuracy is determined by just the accuracy of the photosensitive resist and screen printed ink, it is possible to produce as fine a pattern as will be allowed by the resist resolution.
The above-described printed circuit board structure has the following problems.
Firstly, although the via holes of the multilayer printed circuit board have a conductor on their side walls, because the insides of the via holes are filled with resin, it is not possible to form the other via hole to make an electrical connection to a lower wiring layer or an upper wiring layer, on one via hole, this representing a hindrance in making wiring connections.
Another problem is that, with the method used in the past to fabricate a multilayer printed circuit board, there was poor plating attachment to a via hole formed in the multilayer printed circuit board, thereby lowering the reliability of connections.
Yet another problem was that, with a multilayer printed circuit board of the past, the inside of a via hole is filled with resin, thereby causing a worsening of coplanarity at the resin part, this causing a problem with microfine wiring on the via hole.
Yet another problem was that, with a multilayer printed circuit board of the past, there is generally poor adhesion between the copper plating and the insulating resin material.
Yet another problem was that, when using a via hole of a multilayer printed circuit board as a mounting pad, solder is taken into the via hole, as shown in
FIG. 3
, so that the amount of solder is not constant, thereby making it necessary to provide a separate pad.
The present invention uses additive plating resist and electroless nickel plating in a multilayer printed circuit board, the inside of a via hole being filled with electroless nickel plating, so as to form a flat surface without a hollow part, thereby forming a high-density circuit not possible in the past. This removes the pattern design restriction imposed by the via hole, and enables the achievement of a printed circuit board with a high component mounting density, and high connection reliability.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the present invention has the following basic technical constitution.
The first aspect of the present invention is a multilayer printed circuit board comprising: an insulating board on which an electrical conductive pattern is formed, an insulation layer formed on the insulating board, and a via hole formed in the insulation layer, wherein the via hole is filled with a conductor formed by electroless nickel plating or electroless copper plating.
The second aspect of the present invention is a multilayer printed circuit board comprising: an insulating board on which an electrical conductive pattern is formed, an insulation layer formed on the insulating board, and a via hole formed in the insulation layer, a conductive circuit layer formed on the insulation layer, wherein the via hole and the conductive circuit layer are made of nickel or copper and the insulation layer having the via hole and the conductive circuit layer are formed alternately.
In the third aspect of the present invention, a plating resist as well as the conductive circuit layer is provided on the insulation layer.
The forth aspect of the present invention is a method for manufacturing a multilayer printed circuit board, the multilayer printed circuit board comprising: an insulating board on which an electrical conductive pattern is formed, an insulation layer formed on the insulating board, and a via hole formed in the insulation layer, wherein the via hole is filled with a conductor formed by electroless nickel plating or electroless copper plating.
The fifth aspect of the present invention is a method for manufacturing a multilayer printed circuit board, the multilayer printed circuit board comprising: an insulating board on which an electrical conductive pattern is formed, an insulation layer formed on the insulating board, and a via hole formed in the insulation layer, a conductive circuit layer formed on the insulation layer, wherein the via hole and the conductive circuit layer are formed by electroless nickel plating or electroless copper plating.
The sixth aspec
Hotta Sinichi
Takahashi Hisaya
Alcalá José H.
McGinn & Gibb PLLC
NEC Toppan Circuit Solutions, Inc.
Paladini Albert W.
LandOfFree
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