Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-04-14
2001-10-02
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C174S264000, C174S266000, C361S777000, C361S792000, C361S795000
Reexamination Certificate
active
06297458
ABSTRACT:
BACKGROUND
The disclosures herein relate to computer systems and more particularly, to an apparatus and method for determining printed circuit board process capabilities for use in computer systems.
Multi-layer printed circuit board (hereinafter referred to as PCB) manufacturing and design techniques are well known. In typical PCB designs, there is at least one conductive disk or pad formed on each conductive layer of copper on the inner layers of a PCB. Plated through holes are formed by plating holes formed through a stack of conductive disks or pads. These through holes can be created by mechanical drilling, chemical etching or other techniques.
However, due to manufacturing processing each conductive layer can be misaligned with the plated holes. If a plated hole is misaligned it can break out of the disk and short to adjacent circuitry resulting in a defective board. An unintentional connection within a layer or failure to connect to an intended layer may result in the PCB not performing its intended function. Mis-registration resulting in plated through holes being close to another plated feature but not touching it may also result in adverse performance conditions or increases potential for failure over time.
The design diameter of these disks are determined by the capability of the printed circuit board manufacturer to register plated holes to the conductive disks. In high density printed circuit boards, the size of a plated feature such as plated through hole (hereinafter referred to as PTH) are very small. Due to the tight spacing of plated features in high density PCBs, it is essential that the PTHs be a reliable distance from adjacent plated features. Due to the weight and size requirements of electronic devices, the size of plated through holes in high density PCBs continues to decrease. With this being the case, the potential for one or more of the plated through holes to short to an adjacent plated feature during the fabrication of the PCB also increases. Therefore, it is desirable to determine that the plated through holes are a reliable distance from adjacent plated features prior to integrating the PCB into a related electronic device.
Destructive test methods such as micro-sectioning are commonly used to verify the alignment and spacing of plated features. Destructive test methods are based on statistical sampling processes. They are limited in usefulness and practicality for testing PCBs since every PCB cannot be examined. As there can be thousands of plated through holes in a PCB, the possibility exists that a process condition leading to a defective PCB will not be identified by the statistical sampling process. Furthermore, the cost associated with destructive test methods is proportional to the quantity of samples tested.
Various non-destructive techniques for testing a printed circuit board for misregistration are also known. Some of these techniques simply check for plated features that are unintentionally in contact with or too close to another plated features. These types of techniques can be used for 100% quality inspection, but they do not readily aid in quantifying and improving the printed circuit board manufacturing process capability.
Other types of techniques are intended to determine optimized drilling operation such that the potential for a defective board is minimized. Some of these techniques are based on selecting a drill size. Others are based on selecting an optimized drilling position that minimizes the potential for failure. For many of these techniques, a secondary test operation is still required to determine the statistical probability of a defective PCB. Furthermore, these types of techniques do not readily aid in quantifying and improving the printed circuit board manufacturing process capability.
Accordingly, a need has arisen for a registration test method that overcomes the shortcomings of the previous techniques and, in particular, for an apparatus and method to determine the limitations of a known process for manufacturing PCBs. Incorporation of the apparatus into a PCB may be accomplished by conventional PCB manufacturing processes to support a non-destructive method of quantifying the PCB manufacturing process capability. This method allows for determining the printed circuit board manufacturer's capability to register plated holes relative to the inner conductive layers of a PCB. Accordingly, the design diameter for the pads may be determined.
SUMMARY
One embodiment, accordingly, provides an apparatus for quantifying the PCB manufacturing process capability. This allows the process limitations of the manufacture of the PCB to be better understood and to be utilized in optimizing the design and manufacture of the PCB. To this end, a printed circuit board has a plurality of dielectric substrates laminated in a stacked relationship. Each of the dielectric substrates includes a first and a second surface and has a first conductive layer formed on the first surface. A first pattern of lands is formed in the conductive layer of at least two of the dielectric substrates. The pattern of lands of each dielectric substrate is substantially the same as the first pattern of lands of each other substrate. An opening is formed through each of the lands to expose the respective dielectric substrate. Each of the openings in a respective pattern of lands has a diameter different than at least a portion of the other openings.
An apparatus according to the illustrative embodiments presented herein provides several advantages and benefits. The inherent characteristics of a known process for making a PCB may be quantified. It is also advantageous that a non-destructive method of quantifying the PCB manufacturing process capability may be utilized. Furthermore, incorporation of the apparatus is transparent to the manufacture of the PCB. As such, the apparatus does not impart any extraneous or unintended characteristics to the PCB.
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Khadem Gita
McMillan Thad
Dell USA L.P.
Gaffin Jeffrey
Haynes and Boone L.L.P.
Vigushin John B.
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