Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-03-29
2004-03-23
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000
Reexamination Certificate
active
06710260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer printed circuit board such as a build-up printed circuit board mounted with an electronic component part such as a bare chip, and relates to a manufacturing method of the printed circuit board.
2. Description of the Related Art
Generally, a printed circuit board is utilized for mounting a circuit element such as various kind of electronic component parts in an electronic apparatus. Presently, a printed circuit board is demanded to reduce its dimensions and a circuit pattern is demanded to be finer in accordance with requirements for an electronic apparatus and a circuit element to minimize their dimensions and to integrate them in a high packing density.
Currently, a line width of a circuit pattern and a line pitch between adjoining circuit patterns on a printed circuit board are respectively some 75 &mgr;m. However, as a trend in near future, a finer pattern is demanded for mounting a bare chip directly on a printed circuit board or for packaging a bare chip by utilizing a printed circuit board. Accordingly such line width and line pitch are demanded to be smaller than 40 &mgr;m.
FIGS.
4
(
a
) through
4
(
h
) show each step of manufacturing method of a printed circuit board in accordance with the prior art.
In FIG.
4
(
a
), a metal film such as a copper foil is formed over a core material
1
as an insulative base substrate composed of glass epoxy resin or like. The copper foil is patterned and formed as a first circuit pattern
2
. A line width L
1
and a line pitch L
2
of the first circuit pattern
2
are some 75 &mgr;m minimum and its thickness W
1
is some 20 &mgr;m. A blacking treatment is applied to a surface of the first circuit pattern
2
so as to increase a degree of contact with an insulative layer composed of epoxy resin, which is formed over the surface of the first circuit pattern
2
in a succeeding process.
In FIG.
4
(
b
), an insulative layer
3
is formed all over the surface of the core material
1
by using such a method as a screen-printing. A main ingredient of the insulative layer
3
is epoxy resin. An appropriate amount of inorganic or organic filler
4
of which particle diameter is approximately 10 &mgr;m is mixed in the epoxy resin of the insulative layer
3
and the filler
4
is dissolved during a roughing process, which will be depicted. A thickness of the insulative layer
3
is designed to be 40 to 70 &mgr;m.
In FIG.
4
(
c
), a carbon dioxide laser beam
5
irradiates the insulative layer
3
so as to perforate a hole
6
for connection selectively at a predetermined location and to expose the first circuit pattern
2
. A residue
7
can remain on the surface of the first circuit pattern
2
while perforating the hole
6
by the carbon dioxide laser beam
5
. A diameter of the hole
6
is some 100 &mgr;m.
In FIG.
4
(
d
), by applying alkalescent roughing medicinal solution such as potassium permanganate, the surface of the insulative layer
3
is roughed by forming a plurality of pits
8
with dissolving the filler
4
, which is solvable by the roughing medicinal solution. Further, the residue
7
remaining in the hole
6
as shown in FIG.
4
(
c
) is cleaned up and removed by an action of the potassium permanganate.
In FIG.
4
(
e
), in order to make a foundation for non-electrolytic plating in a succeeding process, a catalyst
9
is adhered to the surface of the insulative layer
4
and the first circuit pattern
2
by applying a solution dissolving tint and palladium, for example, over the surface of the insulative layer
3
and the first circuit pattern
2
so as to increase conductiveness of the surface of all over the insulative layer
3
.
In FIG.
4
(
f
), a first conductive film
10
for electroplating of which main component is copper is formed as a foundation all over the surface of the insulative layer
3
by the non-electrolytic plating, wherein a thickness of the first conductive film
10
is accumulated to approximately 0.3 &mgr;m.
In FIG.
4
(
g
), a second conductive film
11
of copper is formed over the first conductive film
10
by the electroplating process, wherein a thickness of the second conductive film
11
is accumulated to approximately 20 &mgr;m. Accordingly, the first circuit pattern
2
can be electrically connected to the second conductive film
11
. Further, as shown in FIG.
4
(
h
), a second circuit pattern
12
is obtained by etching the second conductive film
11
.
In addition thereto, a third circuit pattern is formed after another insulative layer is formed over the second circuit pattern
11
in a regular manufacturing process. Finally a multi-layer printed circuit board can be manufactured by repeating the processes mentioned above.
In the manufacturing method mentioned above, there existed a problem that forming the line width or line pitch of the circuit pattern
12
as fine as smaller than 40 &mgr;m is hard to realize. Since the diameter of the filler
4
, which is mixed in the insulative layer
3
as a roughing component, is 10 &mgr;m, the diameter is so large that a circuit pattern is hard to be formed linearly and accurately in comparison with the line width and line pitch. In addition thereto, a lower part of a conductor, that is, an anchor part becomes larger to the line width in accordance with a progress of an electronic circuit being activated in a higher speed and higher frequency. Accordingly, an RF (radio frequency) characteristic of the electronic circuit is affected by the skin effect.
To solve the problem, it can be feasible to make the diameter of the filler
4
smaller. However, it can not be adopted by reasons that sufficient peeling off strength of a circuit pattern can not be obtained, or the catalyst
9
of non-electrolytic plating will not penetrate into the pit
8
fully or a manufacturing cost increases.
It is also demanded to reduce the diameter of the hole
6
for connection to smaller than 50 &mgr;m in accordance with the fining demand mentioned above. If the hole diameter is reduced, however, catalyst of non-electrolytic plating or potassium permanganate hardly penetrates into the hole
6
and plating can not be performed sufficiently. Further, residue remaining in the hole
6
can not be removed fully. Accordingly, an electronic connection between the second conductive film
11
formed by electrolytic plating and the circuit pattern
3
can not be maintained sufficiently.
In addition thereto, the manufacturing method mentioned above is a wet type process of utilizing medicinal solution such as alkalescent potassium permanganate and non-electrolytic plating liquid. Accordingly, further problem occurs such that an additional process of washing off medicinal solution is necessary at each time the medicinal solution is applied and effluent must be processed properly.
SUMMARY OF THE INVENTION
Accordingly, in consideration of the above-mentioned problems of the prior art, an object of the present invention is to provide a printed circuit board and a manufacturing method of the printed circuit board, which can effectively manufacture a printed circuit board having an extremely small anchor profile and a finer pattern in few manufacturing processes by utilizing a dry etching method and a film forming method by spattering.
In order to achieve the above object, the present invention provides, according to an aspect thereof, a printed circuit board comprising a circuit pattern formed on a surface of a base substrate of which surface is at least composed of an insulative material, an insulative layer formed over the surface of the base substrate including the circuit pattern and composed of a mixed insulative material of more than two kinds of organic resins having a different etching rate by a dry etching process, a hole for connection perforated on the insulative layer by a laser beam or like, a conductive film for electroplating process as a foundation of electroplating formed on the surface of the insulative layer by a vacuum film forming process after roughing the surface o
Ito Takashi
Mochizuki Shuji
Seki Yasuaki
Connolly Bove & Lodge & Hutz LLP
Norris Jeremy
Talbott David L.
Victor Company of Japan Ltd.
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