Print engine/controller chip with CPU

Details Print engine/controller chip with CPU Print engine/controller chip with CPU

2006-12-12

2006-12-12

Tran, Douglas O. (Department: 2625)

Facsimile and static presentation processing

Static presentation processing

Dot matrix array

C358S001900

Reexamination Certificate

active

07148992

ABSTRACT:
A print engine/controller chip (10) is configurable to be coupled with other like devices to drive a printhead (33). The print engine/controller chip has an interface (27) for receiving compressed page data. Image decoders (28, 88) decode compressed image planes image decoders to perform an expansion, in pipeline fashion, for the received compressed page data. A half-toner/compositer (29) composites respective strips of the decoded image planes and sends output to a printhead interface (32). A printhead interface (32) interfaces with the printhead. A synchronization signal generator (89,90) may output a synchronization signal that is used to synchronize print engine/controllers. One printhead interface (32) preferably acts as master generating the synchronization signal to synchronize all the print engine/controllers to drive the printhead at any one or more of higher speed, higher input resolution, higher outlet resolution or wider format. The print engine/controller is a chip having a micro-controller CPU core.

REFERENCES:
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Derwent Abstract Accession No. 93-286671/36, SU 1762124A (Cyverbetics Inst.) Sep. 15, 1992.

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