Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-27
2004-04-27
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S723000, C438S724000
Reexamination Certificate
active
06727183
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of trench etching that prevents spiking in an ultra low dielectric constant material in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. The damascene and dual damascene processes have become a future trend in metallization. Trenches or vias and trenches are etched in an insulating layer. The trenches or vias and trenches are inlaid with metal to complete the contacts. In order to reduce RC delay to a minimum, low dielectric constant materials are preferably used as the insulating layer. In fact, ultra low dielectric constant.(k) materials are most preferably used. Etch stop layers are often used to accurately form the trenches and vias. For ultra low-k materials (k<2.5), it is very important not to use etch stop layers. If the insulating material has a k value of 2.0, a thin etch stop layer having a k value of about 7.0 will increase the effective k value of the insulating layer to 2.5. Without the etch stop layer, the effective k value is a much more desirable 2.0. However, most of the ultra low-k materials are very porous and have high interstitial doping so that spiking and undercutting happens easily during etching.
FIG. 1A
illustrates spiking
25
in the ultra low-k insulating layer
16
during etching of the damascene opening
20
and undercutting
27
at the interface of the low-k film and the etch stop layer, either in the low-k film or in the etch stop layer. This spiking and undercutting will cause k value damage and unwanted diffusion of the metal layer into the insulating layer through the spiking area
25
. After cleaning, the damaged ultra low-k film may trap the cleaning solvents, further increasing effective k-value. Because of the spiking and trapped solvents, the subsequently deposited barrier layer does not adhere well to the trench surfaces, thereby allowing the metal layer to diffuse into the porous low-k films.
U.S. Pat. No. 6,123,862 to Donohoe et al discloses an etching process for high aspect ratio openings. U.S. Pat. No. 6,156,643 to Chen et al teaches a dual damascene process. U.S. Pat. Nos. 6,159,661 to Huang et al, 6,096,655 to Lee et al, and 6,127,089 to Subramanian et al show dual damascene processes using low dielectric constant materials.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of metallization in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method damascene metallization in the fabrication of integrated circuit devices.
A further object of the invention is to provide a method of damascene metallization using ultra low-k materials.
Yet another object of the invention is to provide a method of preventing spiking and undercutting of an ultra low-k material layer in damascene metallization.
Yet another object of the invention is to provide a novel etch recipe for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization.
In accordance with the objects of this invention a novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is achieved. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.
REFERENCES:
patent: 4563367 (1986-01-01), Sherman
patent: 5562801 (1996-10-01), Nulty
patent: 5632855 (1997-05-01), Jones et al.
patent: 6009830 (2000-01-01), Li et al.
patent: 6013582 (2000-01-01), Ionov et al.
patent: 6096655 (2000-08-01), Lee et al.
patent: 6123862 (2000-09-01), Donohoe et al.
patent: 6127089 (2000-10-01), Subramanian et al.
patent: 6156643 (2000-12-01), Chan et al.
patent: 6159661 (2000-12-01), Huang et al.
patent: 6211092 (2001-04-01), Tang et al.
patent: 6291887 (2001-09-01), Wang et al.
patent: 6312874 (2001-11-01), Chan et al.
patent: 6340435 (2002-01-01), Bjorkman et al.
patent: 6380096 (2002-04-01), Hung et al.
patent: 6399512 (2002-06-01), Blosse et al.
Plummer et al. “Silicon VLSI Technology”, 2000, Prentice Hall, p. 639.
Chao Li-Chih
Liu Jen-Cheng
Ma Ching-Hui
Ackerman Stephen B.
Chen Kin-Chan
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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