Prevention of slurry build-up within wafer topography during...

Details Prevention of slurry build-up within wafer topography during... Prevention of slurry build-up within wafer topography during...

2001-10-23

2002-09-24

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S633000, C438S631000

Reexamination Certificate

active

06455434

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the manufacture of semiconductor devices, and more particularly, to the prevention of slurry build-up within low areas of a substrate topography during polishing.
2. Related Art
FIG. 1
illustrates a related art substrate
10
having topography, in this example, a low area
12
. A first layer
14
is deposited over the substrate
10
, coating the sidewalls
16
and bottom
17
of the low area
12
. Prior to depositing a second layer, the substrate
10
is polished to remove the excess first layer
14
on the surface
18
of the substrate
10
, leaving the first layer
14
only within the low area
12
. However, the polishing material
20
, typically slurry, used during the polishing step often fills the low area
12
, as illustrated in FIG.
2
.
In order to remove the polishing material
20
within the low area
12
, harsh chemicals, such as HF, an Amonium Hydroxide HGL clean, (also known in the industry as “Wang AB”), etc., are often required due to the strong mechanical bonds formed between the polishing material
20
and the first material
14
within the low area
12
. These chemicals can permeate cracks in the substrate
10
, and cause corrosion.
Accordingly, there is a need in the industry for a method that overcomes these and other problems.
SUMMARY OF THE INVENTION
The first general aspect of the present invention provides a method of preventing the build-up of polishing material within at least one low area of a substrate during polishing comprising: blanket depositing a first layer over the substrate; depositing a selectively removable material over the first layer, whereby the selectively removable material fills the at least one low area; polishing the substrate to remove the first layer and the selectively removable material from a surface of the substrate, leaving the first layer and the selectively removable material in the at least one low area; removing the selectively removable material from the at least one low area; and depositing a second layer over the substrate.
The second general aspect of the present invention provides a method of planarizing a substrate having at least one low area, comprising: depositing a first layer over the substrate; depositing a selectively removable material over the first layer; planarizing the substrate leaving the at least one low area, and the first layer and the selectively removable material within the at least one low area; and removing the selectively removable material from the low area.
The third general aspect of the present invention provides a method of planarizing a substrate comprising: depositing a selectively removable material within a low area of the substrate; planarizing a surface of the substrate; and removing the selectively removable material.
The fourth general aspect of the present invention provides a method of planarizing a substrate having at least one low area comprising: filling the low area with a selectively removable material prior to planarizing the substrate to prevent polishing material from building-up within the low area.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.


REFERENCES:
patent: 4963501 (1990-10-01), Ryan et al.
patent: 5718618 (1998-02-01), Guckel et al.
patent: 5980979 (1999-11-01), Rohner
patent: 6013574 (2000-01-01), Hause et al.
patent: 6173240 (2001-01-01), Sepulveda et al.
patent: 6180527 (2001-01-01), Farnworth et al.
patent: 6184138 (2001-02-01), Ho et al.
patent: 6191086 (2001-02-01), Leon et al.
patent: 6194317 (2001-02-01), Kaisaki et al.
patent: 6218316 (2001-04-01), Marsh
patent: 6251789 (2001-06-01), Wilson et al.
patent: 6274483 (2001-08-01), Chang et al.
patent: 6383928 (2002-05-01), Eissa
patent: 2002/0030282 (2002-03-01), Merchant et al.
patent: 2002/0033342 (2002-03-01), Uzoh et al.
patent: 2002/0048959 (2002-04-01), Clevenger et al.
patent: 2002/0055323 (2002-05-01), McClain et al.
patent: 2002/0070126 (2002-06-01), Sato et al.

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