Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1998-07-13
2003-07-15
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S324000, C348S222100
Reexamination Certificate
active
06593966
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to an image pickup apparatus, which prevents noise, caused in a signal processing step, from affecting a video signal.
b) Description of the Related Art
It is well known to use an image scanner, which scans to read subject written material, to take image data into a computer or the like. Lately, it has been studied to use an electronic still camera which can be used to take pictures of a three-dimensional subject. The electronic still camera comprises, for example, a CCD image sensor and its drive circuit, wherein a drive circuit responds to an instruction given by a computer and outputs information charges to be accumulated in a light reception part of the CCD image sensor to obtain a video signal corresponding to the object image.
FIG. 5
is a block diagram showing the structure of a conventional electronic still camera.
FIG. 6
is a diagram showing waveforms of a drive clock for driving a conventional electronic still camera.
A CCD image sensor
1
of a frame transfer method has a light reception part i, a storage part s, a horizontal transfer part h and an output part d. The light reception part i comprises a plurality of shift registers which are arranged continuously in a perpendicular direction and parallel to one another. Respective bits of these shift registers are potentially divided by the action of an electrode to define a plurality of light reception pixels. Thus, the information charges are accumulated in the respective bits of the shift register, namely the light reception pixels, according to the object image irradiated to the light reception part i by an optical system. The storage part s comprises a plurality of shift registers which are connected to the respective shift registers constituting the light reception part i and receives accumulated information charges from the shift registers of the light reception part i. The horizontal transfer part h comprises a single shift register where each bit is related to the output end of the shift registers of the storage part s and outputs so as to sequentially transfer the information charges received on a horizontal line basis from the storage part s. The output part d is disposed on the output side of the horizontal transfer part h and converts the information charges output from the horizontal transfer part h into a voltage value on a pixel basis, for output as a video signal y
0
(
t
).
An analog processing circuit
2
performs processing, such as sample and hold or level clamp, of a video signal y
0
(
t
) which is input from the CCD
1
to produce a video signal y
1
(
t
) conforming to a predetermined format. For example, in the sample-and-hold processing, only a signal level is taken out of the video signal y
0
(
t
) which has a reset level and a signal level alternately repeated in synchronization with the operation of the output part d of the CCD
1
. In the level-clamp processing, a black reference level determined at the end of a horizontal scanning period of the video signal y
0
(
t
) is clamped to a predetermined level for every horizontal scanning period.
An A/D conversion circuit
3
quantizes the video signal y
1
(
t
) input from the analog processing circuit
2
at a timing according to the operation of the analog processing circuit
2
, namely the output operation of the CCD
1
, and produces video data D
1
(
n
) which indicates, in a digital value, information corresponding to the individual light reception pixel of the light reception part i. A digital processing circuit
4
performs processing such as color separation and matrix operation of video data D
1
(
n
) input from the A/D conversion circuit
3
to produce video data D
2
(
n
) containing luminance information and color difference information. For example, the color separation process divides video data D
1
(
n
) according to a color arrangement of a color filter fitted to the light reception part i of the CCD
1
to produce multiple items of color component information. The matrix operation process synthesizes the divided color components to produce luminance information and also picks up luminance information from the individual color component information to produce color difference information. Video data D
2
(
n
) output from the digital processing circuit
4
is supplied to a computer in conformity with a given output format.
In response to various timing signals from the timing control circuit
6
, the drive circuit
5
supplies polyphase drive clocks to each part of the CCD
1
. For example, the drive circuit
5
supplies quadrature phase transfer clocks &phgr;v, &phgr;s to the light reception part i and the storage part s and binary transfer clock &phgr;h to the horizontal transfer part h. A vertical transfer clock &phgr;v has a discharge pulse for discharging all information charges accumulated in the light reception part i and a read-out pulse for transferring information charges for a single screen of the light reception part i as shown in
FIG. 6. A
storage transfer clock &phgr;s has a read-in pulse corresponding to a read-out pulse of the vertical transfer clock &phgr;v and a line-spacing pulse for transferring information charges of the storage part s to the horizontal transfer part h for every horizontal line. The horizontal transfer clock &phgr;h has an output pulse for transferring an information charge for a single line of the horizontal transfer part h to the output part d. Thus, the information charges accumulated in the light reception part i during a period from the end of the discharge pulse to the start of the read-out pulse are transferred from the light reception part
1
to the storage part s for temporary storage, and output for transfer in a single line unit from the storage part s via the horizontal transfer part h.
In response to an image-pickup instruction P and a transfer instruction T supplied from the computer, the timing control circuit
6
produces timing signals RT, VT, HT to designate timing of each transfer drive conducted by the CCD
1
and supplies them to the drive circuit
5
. At the same time, a reference clock CK is supplied to the analog processing circuit
2
, the A/D conversion circuit
3
and the digital processing circuit
4
to synchronize the operation of the individual circuit with the output operation of the CCD
1
. The discharge timing signal RT, responding to the image-pickup instruction P, gives an instruction to the drive circuit
5
to produce a discharge pulse of a vertical transfer clock &phgr;v. The vertical transfer timing signal VT is delayed for an exposure period with respect to the discharge timing signal RT and gives an instruction to the drive circuit
5
to produce a discharge pulse of the vertical transfer clock &phgr;v and a read-in pulse of the storage transfer clock &phgr;s. In response to the transfer instruction T, the horizontal transfer timing signal HT gives an instruction to the drive circuit
5
to produce a line-spacing pulse of a storage transfer clock &phgr;s and an output pulse of a horizontal transfer clock &phgr;h. The horizontal transfer timing signal HT is configured so that a single line-spacing pulse and an output pulse are produced by a single trigger or a plurality of line-spacing pulses and output pulses are produced at an equal interval by a single trigger.
With such an electronic still camera, a desired object image is taken in response to the image-pickup instruction P, and video data D
2
(
n
) showing the object image is output in response to the transfer instruction T.
Where video data is taken into a computer through an electronic still camera, the computer's internal processing is temporarily stopped so as to allow input of the video data. If video data having a large information quantity is continuously entered into the computer for a single screen, it takes a longer time to stop the internal processing. Therefore, video data is generally entered in a single line unit in conformity with the processing capacity of each part of the computer. An imag
Garber Wendy R.
Hogan & Hartson LLP
Sanyo Electric Co,. Ltd.
Ye Lin
LandOfFree
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