Preventing drain to body forward bias in a MOS transistor

Details Preventing drain to body forward bias in a MOS transistor Preventing drain to body forward bias in a MOS transistor

2011-06-28

2011-06-28

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S333000, C327S543000, C327S546000

Reissue Patent

active

RE042494

ABSTRACT:
A voltage level shifting circuit (FIG.4) has a plurality of PMOS transistors M1, M2, M3connected in parallel for respectively driving a capacitive load CLwith a selected different voltage level V1, V2or V3. Transistors M1, M2, M3are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2or V3to charge the load CL. The largest voltage transistor M3has its body connected to its source. The lower voltage transistors M1, M2have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3when the transistors are placed in the OFF condition.

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patent: 5552723 (1996-09-01), Shigehara et al.
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patent: 6232793 (2001-05-01), Arimoto et al.
patent: 7492215 (2009-02-01), Lee et al.
patent: 07-086917 (1995-03-01), None

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