Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-08-20
2001-04-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290, C365S185300
Reexamination Certificate
active
06212099
ABSTRACT:
FIELD OF THE INVENTION
This invention is generally related to memory devices and more particularly to techniques for preventing the corruption of data stored in flash memory devices.
BACKGROUND
Flash memory devices are used in a wide range of electronic systems that require reliable, non-volatile storage and retrieval of large amounts of data at low cost. A conventional flash memory device
300
as illustrated in
FIG. 3
includes thousands of cells arranged in an array
304
. Each cell can be configured to respond with a logical “0” or logical “1”, and will maintain its state with the power off. A controller
308
operates by executing instructions that are provided by internal microcode
312
and by external commands received over an address bus
324
and a control bus
328
. The controller
308
generates control signals
316
that cause read/write path circuitry
320
to “program” selected cells from a logical 0 state into a logical 1 state in accordance with data received over a data bus
332
where all cells had previously been “erased” into a logical 0 state. This data that has been stored in the cells can thereafter be read by issuing a read command to the controller
308
. To explain the data corruption problem, some flash memory operations and part of a typical flash memory cell array
304
shown in
FIG. 4
are described.
The portion of a flash memory cell array in
FIG. 4
features a number of blocks 0 . . . N that are built in the substrate of an integrated circuit die. In this version, the blocks repeat horizontally along a number of global wordlines GL
1
, GL
2
, . . . GL
M
. A number of cells are formed in each block. The gate terminals of all cells in a horizontal row are connected to the same, conducting, local wordline. The drain terminals of all cells in a vertical column are connected to the same, conducting, bitline. The drain, source and gate terminals of each cell are subjected to different voltages through high voltage conditioning circuitry (not shown) which causes a floating gate in each cell to exhibit different levels of charge, depending upon whether the cell is being programmed or erased. The amount of charge on the floating gate in part determines the state (0 or 1) of the cell.
FIG. 4
shows the source terminals being coupled to the power supply/ground node (through control circuitry which is not shown) such as during program, read, or idle conditions.
Each global wordline GL
i
is coupled to a local wordline of a block through a switch SW
i
being a p-channel metal oxide semiconductor (MOS) field effect transistor (FET), such as the one shown in FIG.
5
. This p-channel MOSFET is used as a switch to select or not select a block for erasing or programming. When V
BS
# is asserted, the p-channel MOSFETs can conduct to apply the voltages on the global wordlines to their corresponding local wordlines in the selected block. When V
BS
# is deasserted, the MOSFETs are cut off such that their associated local wordlines are floating. In practice, the p-channel MOSFETs for a given block are formed in a continuous n-type tub (also known as a “well”) in a p-type semiconductor substrate. The electrical path to the n-type tub is represented by the fourth terminal of the MOSFET symbol, which is also known as the bulk terminal. To make more efficient use of the real estate available on the flash memory die and to simplify the control circuitry needed for its operation, two or more tubs on the die are shorted to each other and connected to a bulk voltage V
B
. For the same reasons, the gates of all of the p-channel MOSFETs associated with the same block are shorted together and receive the same control signal V
BS
#.
Since the local wordlines LL1 . . . . LLM of an unselected block are floating, and the global wordlines GL1 . . . GLM can take on a range of voltages (e.g., 0-10 V) during an erase operation, the bulk terminal of each MOSFET is set to a sufficiently high voltage V
B
(e.g., 10 V) for proper operation as a switch, to ensure that the drain-bulk junction and the source-bulk junction of the MOSFET are never forward biased.
The erase operation in a flash memory device is typically performed one block at a time, where a block is selected by asserting its V
BS
#, while the V
BS
# for the other unselected blocks remains deasserted. To avoid uneven erasure between cells, the erase operation is typically preceded by a conditioning step, sometimes referred to as “preconditioning”, in which the floating gate in each of the cells in the selected block is charged up to the same level. During conditioning of a block, a relatively high voltage is asserted on a global wordline and its associated local wordline, while each bitline in the selected block is pulsed with a bitline conditioning voltage. This is done until all cells coupled to that wordline have been charged to the same level. The operation is repeated for all global wordlines that cross the selected block, so that the entire block will be charged to the same level. The block can then be uniformly erased.
The data stored in some of the cells of an unselected block in the flash memory device described above can become corrupted, i.e., a logical 0 can be transformed into a logical 1 and vice versa, after a given number of block erase operations have been performed. The data corruption tends to worsen at elevated operating temperatures, which suggests that a charge leakage phenomenon may be at fault. Generally, charge leakage may be reduced by clever circuit design or improvements to the semiconductor manufacturing process. However, such changes can be relatively expensive to implement because they involve making changes to the manufacturing production line for the flash memory device. Accordingly, there is a need for a less costly technique to remedy the above-described data corruption problem.
SUMMARY
An embodiment of the invention is directed to a method of operating a flash memory, by discharging at least one wordline, that is coupled to a first set of flash memory cells, during an interval in which a second set of flash memory cells are being conditioned, such that the at least one wordline does not develop a charge that is sufficient to corrupt the data stored in the first set.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 5572707 (1996-11-01), Rozman et al.
patent: 5748528 (1998-05-01), Campardo et al.
patent: 5748939 (1998-05-01), Rozman et al.
patent: 5886923 (1999-03-01), Hung
patent: 5907700 (1999-05-01), Talreja et al.
patent: 5978275 (1999-11-01), Song et al.
Annavajjhala Ravi
Baltar Robert L.
Landgraf Marc E.
Wong Dow-Ping D.
Zhang Suibin
Auduong Gene
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nelms David
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