Pressure contact chip and wafer testing device

Details Pressure contact chip and wafer testing device Pressure contact chip and wafer testing device

1993-05-18

1995-02-14

Wieder, Kenneth A.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324754, G01R 104

Patent

active

053898737

ABSTRACT:
In order to enable a burn-in test in a wafer state even if a semiconductor wafer has a number of bonding pads on every chip, bumps (15) are brought into contact with bonding pads (5c) of all chips (5b) provided on a semiconductor wafer (5), so that voltages are simultaneously applied to all chips. The bumps (15) are arranged on a translucent polyimidc film (10) in mirror image relation to the bonding pads (5c), so that the former are aligned with the latter with alignment marks (34a, 34b) through an opening (11a) and the polyimide film (10) with a light-optic microscope (13). A heater (14) is brought into dose contact with the back surface of the semiconductor wafer (5), to heat the same. Thus, potential defective chips can be screened before assembling steps, to reduce the cost. Failure analysis can be quickly performed with excellent maintenance on a process line, to improve the yield and the throughput.

REFERENCES:
patent: 4065717 (1977-12-01), Kattner et al.
patent: 5065103 (1991-11-01), Slinkman
IEEE/IRPS, J. Mitsuhashi, et al., 1987, "Effect of P-Sin Passivation Layer on Time-Dependent Dielectric Breakdown in SiO2", pp. 60-65.

Affiliated with

Also associated with

Rating

Pressure contact chip and wafer testing device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pressure contact chip and wafer testing device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pressure contact chip and wafer testing device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-290086