Preset circuit for a clocked flip-flop

Details Preset circuit for a clocked flip-flop Preset circuit for a clocked flip-flop

1982-03-23

1984-05-15

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307479, 307443, H03K 19003, H03K 3037, H03K 1730

Patent

active

044490607

ABSTRACT:
A preset circuit for a flip-flop of set priority type having set and reset terminals both being intended for preset function and wherein data "1" is preset where both of terminals are enabled and only the set terminal is enabled, data "0" is preset where only the reset terminal is enabled, and usual operation is achieved where both of terminals are disabled causes both of set and reset terminals to be enabled where data "1" is to be preset. The preset circuit supplies data input to the set terminal through a NOR gate which uses the signal supplied to the reset terminal as a gate signal.

REFERENCES:
patent: 3515998 (1970-06-01), Adams et al.
patent: 3603816 (1971-09-01), Podraza
patent: 3673434 (1972-06-01), McIntosh
patent: 4001611 (1977-01-01), Maruyama et al.
C.sup.2 MOS Integrated Circuits Technical Data, First Edition, Jan. 1981, Toshiba Corporation, Tokyo, Japan.

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