Prescaler and PLL circuit

Details Prescaler and PLL circuit Prescaler and PLL circuit

2000-09-22

2002-10-15

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S231000, C327S159000, C331S025000

Reexamination Certificate

active

06466065

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a prescaler and a PLL circuit, and more specifically, to a PLL circuit that matches an output signal frequency with a predetermined frequency.
Phase-locked loop (PLL) circuits are used in mobile communication devices, such as cellular telephones. To improve the performance of the mobile communication device, a PLL circuit must quickly shift an output signal frequency to the desired frequency. Accordingly, it is required that the lockup time of the PLL circuit be decreased.
FIG. 1
is a schematic block diagram showing a prior art PLL circuit. The PLL circuit includes an oscillator
1
, which generates a reference clock signal CK having an inherent frequency corresponding to the oscillation of a crystal oscillating element. The clock signal CK is provided to a reference frequency divider
2
. The reference frequency divider
2
includes a counter circuit, divides the frequency of the reference clock signal CK in accordance with a division ratio determined by a shift register
3
to generate a reference signal fr, and provides the reference signal fr to a phase comparator
4
.
The phase comparator
4
provides a charge pump
6
with pulse signals &PHgr;R, &PHgr;P corresponding to the frequency difference or phase difference between the reference signal fr and a comparison signal fp.
The charge pump
6
provides an output signal SCP corresponding to the pulse signals &PHgr;R, &PHgr;P to a low-pass filter (LPF)
7
.
The output signal SCP has DC components, which include pulse components. The DC components shift in accordance with the frequency fluctuation of the pulse signals &PHgr;R, &PHgr;P, and the pulse components shift in accordance with the phase difference of the pulse signals &PHgr;R, &PHgr;P.
The LPF
7
smoothes and eliminates high frequency components from the output signal SCP of the charge pump
6
to generate an output signal SLPF, which is provided to a voltage-controlled oscillator (VCO)
8
.
The VCO
8
generates an oscillation output signal fvco, which has a frequency corresponding to the voltage value of the output signal SLPF of the LPF
7
, and provides the oscillation output signal fvco to an external circuit and a comparison frequency divider
5
.
The comparison frequency divider
5
is a pulse-swallow type, and includes a prescaler
9
, a main counter
10
, a swallow counter
11
, and a control circuit
12
.
The prescaler
9
divides the frequency of the input signal (the oscillation output signal fvco of the VCO
8
) by M or by (M+1) to generate a prescaler divisional signal Pout. Then, the prescaler
9
provides the prescaler divisional signal Pout to the main counter
10
and the swallow counter
11
.
The swallow counter
11
divides the prescaler divisional signal Pout by A and provides a swallow counter divisional signal to the control circuit
12
. In accordance with the swallow counter divisional signal, the control circuit
12
provides the prescaler
9
with, for example, a high module control signal MD. In accordance with the module control signal MD, the prescaler
9
divides the frequency of the oscillation output signal fvco by M to output the prescaler divisional signal Pout.
While the swallow counter
11
is counting an A number of pulses, the control circuit
12
provides the prescaler
9
with, for example, a low module control signal MD. In accordance with the module control signal MD, the prescaler
9
divides the frequency of the oscillation output signal fvco by (M+1) to output the prescaler divisional signal Pout.
The shift register
3
determines a division ratio N of the main counter
10
. The main counter
10
divides the frequency of the prescaler divisional signal Pout by N to generate the comparison signal fp and provides the comparison signal fp to the phase comparator
4
. The divisional signal (comparison signal) fp of the main counter
10
is also provided to the control circuit
12
. The control circuit
12
provides the swallow counter
11
with an activation signal each time the main counter
10
divides the frequency of the prescaler divisional signal Pout by N.
Accordingly, every time the main counter
10
divides the prescaler divisional signal Pout by N in the above PLL circuit, the swallow counter
11
is activated and the prescaler divisional signal Pout is counted.
FIG. 2
is a schematic circuit diagram showing the prior art prescaler
9
. The oscillation output signal fvco of the VCO
8
is input to synchronous flip-flop circuits FF
1
, FF
2
, FF
3
, which form a frequency division shifting circuit C, as input signals CK, XCK through a buffer circuit
13
. It is preferred that each of the flip-flop circuits FF
1
-FF
3
be a D flip-flop (delay flip-flop) circuit.
The flip-flop circuit FF
1
provides output signals QH, XQH as data XD, D, respectively, to the flip-flop circuit FF
2
. The flip-flop circuit FF
2
provides its QH output signal to a first input terminal of an OR circuit
14
a
and its XQH output signal to a first input terminal of an OR circuit
14
b.
The OR circuit
14
a
provides an output signal as data to the flip-flop circuit FF
1
. The OR circuit
14
b
provides an output signal as data to the flip-flop circuit FF
3
. The flip-flop circuit FF
3
provides its output signal XQH to a second input terminal of the OR circuit
14
a.
Two T-type flip-flop circuits TFF
1
, TFF
2
, which form an asynchronous extender circuit E, are provided. The flip-flop circuit FF
1
provides its XQ output to the flip-flop circuit TFF
1
as its CK input signal.
The flip-flop circuit TFF
1
provides its output signal Q as the input signal CK to the flip-flop circuit TFF
2
. The flip-flop circuit TFF
2
provides its output signal Q to a buffer circuit
15
. The buffer circuit
15
outputs the prescaler divisional signal Pout.
A bias circuit
16
provides the input signal XCK, which has a constant voltage, to the flip-flop circuits TFF
1
, TFF
2
.
The output signals QH of the flip-flop circuits TFF
1
, TFF
2
are provided to first and second input terminals of an OR circuit
14
c
. A third input terminal of the OR circuit
14
c
is provided with the module control signal MD. The OR circuit
14
c
provides its output signal OR to a second input terminal of the OR circuit
14
b.
The flip-flop circuits TFF
1
, TFF
2
are each configured as shown in FIG.
3
. The flip-flop circuits TFF
1
, TFF
2
each invert the output signal Q and complementary output signals QH, XQH whenever the clock signal CK goes high. Accordingly, the flip-flop circuits TFF
1
, TFF
2
divide the output signal XQ of the flip-flop circuit FF
1
by four.
FIG. 4
is a timing chart showing the operation of the prescaler
9
. When the prescaler
9
is provided with the oscillation output signal fvco of the VCO
8
, the operation of the flip-flop circuits FF
1
, FF
2
causes the flip-flop circuit FF
1
to divide the oscillation output signal fvco by four and generate the output signal XQ.
The output signal Q of the flip-flop circuit TFF
1
is generated by dividing the output signal XQ of the flip-flop circuit FF
1
by two, that is, by dividing the oscillation output signal fvco by eight. Further, the output signal Q of the flip-flop circuit TFF
2
is generated by dividing the oscillation output signal fvco by sixteen.
When the module control signal MD is low, the output signal OR of the OR circuit
14
c
is determined by the QH output signals of the flip-flop circuits TFF
1
, TFF
2
.
Until the prescaler
9
counts twelve pulses of the oscillation output signal fvco from a count initiation point SP, at least one of the output signals QH of the flip-flop circuits TFF
1
, TFF
2
is high. Thus, the output signal OR of the OR circuit
14
c
is high. In this state, the output signal XQH of the flip-flop circuit FF
3
is fixed at a low level.
When the prescaler
9
counts twelve pulses of the oscillation output signal fvco, the output signals QH of the flip-flop circuits TFF
1
, TFF
2
both go low. Thus, the output signal OR of the OR circuit
14
c
goes low. In this state, the flip-flop circuit FF

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