Prescalar using fraction division theory

Details Prescalar using fraction division theory Prescalar using fraction division theory

2000-12-01

2002-04-30

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C377S048000

Reexamination Certificate

active

06380773

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a prescalar. More particularly, the invention relates to prescalar using fraction division theory.
2. Description of the Related Art
A conventional prescalar comprises a two mode frequency divider synchronously divided by ⅘ and a circuit non-synchronously divided by 16. The minimum amplitude signal output by a bias control oscillator can be converted into a large pushable digital logic signal. At the front end of the circuit, an input amplifier is typically installed. While adapting such high speed logic in dynamic logic, the maximum operation frequency is not restricted by the operation speed of the logic circuit, but the frequency response of the input amplifier. When the frequency response of input amplifier is directly determined by the load capacitor, that is, by the input capacitance load of the logic circuit portion of the prescalar, the synchronous frequency divider is normally constructed of three circuits divided by 2. That, the synchronous frequency divider includes three flip flops. For the input amplifier, the load is the clock load of the three flip flops.
SUMMARY OF THE INVENTION
The invention provides a prescalar using fraction division theory. An input amplifier only drives one divided-by-2 circuit, that is, the load thereof is a clock load of a single flip flop. Therefore, a higher frequency response of the input amplifier can be obtained compared to the conventional structure. As a result, the maximum operation frequency of the prescalar can be enhanced.
The invention uses a divided-by-2 circuit divided and a synchronously divided-by-{fraction (2/2.5)} two mode frequency divider to replace the conventional two mode frequency divided by ⅘, and a non-synchronously divided-by-{fraction (16/13)} two mode frequency divider and an input amplifier. The divided-by-{fraction (2/2.5)} two mode frequency divider synchronously comprises a divisor selection circuit, a plurality translucent circuits and a synthesized divided-by-{fraction (2/2.5)} logic circuit. The non-synchronously divided-by-{fraction (16/13)} two mode frequency divider comprises a reset flip flop, an erase flip flop and a reset control logic NOR gate.
The divisor selection circuit of the two mode frequency divider synchronously divided by {fraction (2/2.5)} comprises a first to a sixth transistors. The first transistor comprises a gate coupled to an input terminal IN. A drain of the second transistor is coupled to a source of the first transistor. A drain of the fourth transistor is coupled to the source of the first transistor. The drain of the third transistor is coupled to a source of the second transistor. A drain of the fifth transistor is coupled to a source of the fourth transistor. A source region of the third transistor is coupled to a source of the fifth transistor. A drain of the sixth transistor is coupled to a source of the fifth transistor. A gate of the sixth transistor is coupled to the input terminal. A source of the sixth transistor is coupled to ground.
The translucent circuits of the synchronously divided-by-{fraction (2/2.5)} two mode frequency divider comprises the seventh to the thirty-second transistors. A drain of the eighth transistor is coupled to a source of the seventh transistor. A gate of the tenth transistor is coupled to the drain of the eighth transistor. A drain of the ninth transistor is coupled to a source of the eighth transistor. A gate of the ninth transistor is coupled to a gate of the seventh transistor. A source of the ninth transistor is grounded. A gate of the eleventh transistor is coupled to a gate of the eighth transistor. A drain of the eleventh transistor is coupled to a source of the tenth transistor. A drain of the twelfth transistor is coupled to a source of the eleventh transistor. A source of the twelfth transistor is grounded. A gate of the twelfth transistor is coupled to the drain of the eighth transistor. A gate of the thirteenth transistor is coupled to the drain of the twelfth transistor. A drain of the fourteenth transistor is coupled to a source of the thirteenth transistor. A gate of the fourteenth transistor is coupled to the gate of the eleventh transistor. A gate of the fifteenth transistor is coupled to the gate of the thirteenth transistor. A source of the fifteenth transistor is grounded. A gate of the sixteenth transistor is coupled to the drain of the fourteenth transistor. A gate of the seventeenth transistor is coupled to a gate of the fourteenth transistor. A drain of the seventeenth transistor is coupled to a source of the sixteenth transistor. A gate of the eighteenth transistor is coupled to the drain of the fourteenth transistor. A source of the eighteenth transistor is grounded. A drain of the eighteenth transistor is coupled a source of the seventeenth transistor. A gate of the nineteenth transistor is coupled to a drain of the eighteenth transistor. A drain of the twentieth transistor is coupled to a source of the nineteenth transistor. A gate of the twentieth transistor is coupled to the gate of the seventeenth transistor. A gate of the twenty-first transistor is coupled to the gate of the nineteenth transistor. A source of the twenty-first transistor is coupled to ground. A gate of the twenty-second transistor is coupled to the drain of the twentieth transistor. A gate of the twenty-third transistor is coupled to the gate of the twentieth transistor. A drain of the twenty-third transistor is coupled to a source of the twenty-second transistor. A gate of the twenty-fourth transistor is coupled to the drain of the twentieth transistor. A source of the twenty-fourth transistor is connected to ground. A drain of the twenty-fourth transistor is coupled to a source of the twenty-third transistor. A drain of the twenty-fifth transistor is coupled to a drain of the twenty-fourth transistor. A gate of the twenty-fifth transistor is coupled to ground. A gate of the twenty-sixth transistor is coupled to a drain of the twenty-fifth transistor. A drain of the twenty-seventh transistor is coupled to a source of the twenty-sixth transistor. A gate of the twenty-seventh transistor is coupled to the gate of the twenty-third transistor. A gate of the twenty-eighth transistor is coupled to the gate of the twenty-sixth transistor. A source of the twenty-eighth transistor is coupled to ground. A gate of the twenty-ninth transistor is coupled to drain of the twenty-seventh transistor. A gate of the thirtieth transistor is coupled to the gate of the twenty-seventh transistor. A drain of the thirtieth transistor is coupled to a source of the twenty-ninth transistor. A gate of the thirty-first transistor is coupled to the drain of the twenty-seventh transistor. A source of the thirty-first transistor is coupled to ground. A drain of the thirty-first transistor is coupled to a source of the thirtieth transistor. A drain of the thirty-second transistor is coupled to the drain of the thirty-first transistor. A gate of the thirty-second transistor is coupled to the gate of the twenty-fifth transistor. A source of the thirty-second transistor is grounded.
The synthesized divided-by-{fraction (2/2.5)} logic circuit of the synchronously-divided-by-{fraction (2/2.5)} two mode frequency divider comprises a first NAND logic gate, a second NAND logic gate, a third NAND logic gate, a multiplexer and a NOT logic gate. The second NAND logic gate comprises a second input terminal coupled to an output terminal of the first NAND logic gate. An output terminal of the third NAND logic gate is coupled to a second input terminal of the second NAND logic gate. An output terminal of the multiplexer is coupled to a first output terminal of the third NAND logic gate. A first terminal of the NOT logic gate is coupled to a second input terminal fo the third NAND logic gate.
The non-synchronously divided-by-{fraction (16/13)} two mode frequency divider comprises a first flip flop to a fifth flip flop and a NOR logic gate. The first flip flop comprises a first input ter

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