Preparing instruction groups for a processor having multiple...

Details Preparing instruction groups for a processor having multiple... Preparing instruction groups for a processor having multiple...

2011-04-26

2011-04-26

Yigdall, Michael J (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C712S215000, C712S200000, C712S206000

Reexamination Certificate

active

07934203

ABSTRACT:
During program code conversion, such as in a dynamic binary translator, automatic code generation provides target code21executable by a target processor13. Multiple instruction ports610disperse a group of instructions to functional units620of the processor13.Disclosed is a mechanism of preparing an instruction group606using a plurality of pools700having a hierarchical structure711-715. Each pool represents a different overlapping subset of the issue ports610. Placing an instruction600into a particular pool700also reduces vacancies in any one or more subsidiary pools in the hierarchy. In a preferred embodiment, a counter value702is associated with each pool700to track vacancies. A valid instruction group606is formed by picking the placed instructions600from the pools700. The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimized or completely avoided.

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