Preparation of passivated chip-on-board electronic devices

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support

Reexamination Certificate

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C438S127000, C029S527200, C029S841000, C029S855000

Reexamination Certificate

active

06573124

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to electronic devices, and, more particularly, to the protection of such devices against damage from external environmental effects.
Microelectronic devices are typically fabricated as an array of active and passive elements on a substrate, sometimes termed a die. The electronic elements may be in planar microchip form or discrete elements, or both. The die must be supported, and, for some applications, the electronic elements protected against physical and chemical damage arising from external sources.
In one widely used approach, the device is encapsulated inside a hermetically sealed package, made of a material such as aluminum oxide, and having electrical leads extending through the walls of the package. The package protects the device against extremely aggressive physical and chemical environments. On the other hand, package structures are relatively expensive, heavy, and bulky. It may be difficult and time consuming to make the attachments to the electrical leads. The packages are potentially subject to leaking over the course of their service lives. Replacement or repair of devices within the package is difficult.
In another approach, the die is mounted to a printed circuit board, and the electrical interconnections are achieved using wirebonding procedures. This approach is quite popular and is used in many consumer electronics products. Manufacturing costs are considerably lower than for packaged devices, size and weight are reduced, and components may be easily tested and replaced if necessary during fabrication or service. This latter approach has the disadvantage that the electronic device is not well protected against external influences such as corrosion. For most consumer products, the corrosive effects are of relatively minor significance, as failed devices may be readily replaced.
Electronic devices placed into space aboard satellites or other spacecraft must remain reliable for many years. The ambient atmosphere in space is relatively benign in respect to corrosion. The protection afforded by hermetic packages is not required and is preferably not utilized due to the other disadvantages of hermetic packages, but it is necessary to provide a moderate degree of protection. Additionally, the device and its protection must withstand the loads and vibrations produced during the launch and maneuvering of the spacecraft.
There is a need for an improved approach to the support, interconnection, and passivation of electronic devices for use in environments which are relatively benign in respect to corrosion. The present invention fulfills this need, and further provides related advantages.
SUMMARY OF THE INVENTION
The present invention provides a method of preparing an electronic device assembly having a die mounted to a support, termed a “chip-on-board” device. The device is relatively inexpensive in its support approach, yet provides a moderate degree of protection for the electronic components that is fully sufficient for many applications such as spacecraft electronics. The protective technique is compatible with the use of fine-wire wirebonds, wherein the wires are about 0.001 inch in diameter or smaller in size. The protection is inexpensive and readily furnished, adds little weight, and permits repair and/or replacement of components as may be necessary.
In accordance with the invention, a method of preparing a chip-on-board electronic device assembly comprises the steps of providing an electronic device die having an electronic circuit element thereon, wherein the electronic circuit element has a die electrical bonding pad thereon, and providing a printed circuit board having a circuit board electrical bonding pad thereon. The die is affixed to the printed circuit board. At least a portion of the die is coated with a layer of silicon oxynitride, and the die electrical bonding pad and the circuit board electrical bonding pad are electrically interconnected with a wire. The coating is performed before the die is affixed to the printed circuit board.
Optionally but preferably, a thin layer of a conformal coating material such as parylene is applied overlying the layer of silicon oxynitride. The coating is preferably from about 0.1 to about 0.5 micrometers thick, and is applied by a technique such as plasma enhanced chemical vapor deposition (PECVD) that does not disturb the wires of the wirebonds.
In a variation of this approach, the die electrical bonding pad and the circuit board electrical bonding pad are electrically interconnected with a fine wire having a diameter of less than about 0.001 inches. Thereafter, the die is coated with a layer of an organic protective coating. The coating is accomplished by forming a mist of the material of the organic protective coating, and depositing the mist onto the die. The fine wire of the wirebond is not disturbed or bent, yet is protected. A thin layer of a conformal coating material such as parylene may be applied over the organic protective coating.
This approach to preparing a chip-on-board electronic device provides an electronic device that is relatively inexpensive to mount and protect, but is fully suitable for spacecraft and other applications where a relatively modest degree of corrosive attack is expected, the device must withstand relatively severe loadings and vibrations, yet weight and volume must be low. Other features and advantages of the present invention will be apparent from the following more detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. The scope of the invention is not, however, limited to this preferred embodiment.


REFERENCES:
patent: 4173664 (1979-11-01), Cieloszyk
patent: 4953005 (1990-08-01), Carlson et al.
patent: 5086018 (1992-02-01), Conru et al.
patent: 5151559 (1992-09-01), Conru et al.
patent: 5274913 (1994-01-01), Grebe
patent: 5475417 (1995-12-01), Ogata et al.
patent: 5506446 (1996-04-01), Hoffman et al.
patent: 5622898 (1997-04-01), Zechman
patent: 5656830 (1997-08-01), Zechman
patent: 5753974 (1998-05-01), Masukawa
patent: 5824568 (1998-10-01), Zechman
patent: 5851664 (1998-12-01), Bennett et al.
patent: 5928598 (1999-07-01), Anderson et al.
patent: 5945605 (1999-08-01), Julian et al.
patent: 5951813 (1999-09-01), Warren
patent: 6037044 (2000-03-01), Giri et al.
patent: 6110537 (2000-08-01), Heffner et al.
patent: 6140144 (2000-10-01), Najafi et al.
patent: 6184121 (2001-02-01), Buchwalter et al.
patent: 6245663 (2001-06-01), Zhao et al.
patent: WO 92/17905 (1992-10-01), None
patent: 3-171655 (2001-07-01), None

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