Prenormalization for a floating-point adder

Details Prenormalization for a floating-point adder Prenormalization for a floating-point adder

1989-02-14

1991-04-23

Malzahn, David H.

Boots, shoes, and leggings

36471504, G06F 501, G06F 750

Patent

active

050105086

ABSTRACT:
In a floating-point subtraction of two numbers where a normalized result is needed, a prenormalization circuit predicts the number of leading zeroes which will appear in the resultant mantissa, due to the close value of the two source operands. The prenormalization circuit then causes appropriate left shifts of the two operand mantissas prior to the subtraction (two's complement addition) is performed, wherein the resultant mantissa will already be normalized.

REFERENCES:
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4779220 (1988-10-01), Nukiyama
patent: 4905178 (1990-02-01), Mor et al.
patent: 4922446 (1990-05-01), Zurawski et al.
ANSI/IEEE, IEEE Standard for Binary Floating-Point Arithmetic, Aug. 12, 1986.

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