Premature termination of microcontroller EEPROM write

Static information storage and retrieval – Addressing

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Details

364483, 364228, 395425, 371 151, 371 291, G06K 500

Patent

active

053512162

ABSTRACT:
A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

REFERENCES:
patent: 4467434 (1984-08-01), Hurley et al.
patent: 4734568 (1988-03-01), Watanabe
patent: 4798941 (1989-01-01), Watanabe
patent: 4813024 (1989-03-01), Lisimague et al.

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