Preload test circuit for programmable logic arrays

Details Preload test circuit for programmable logic arrays Preload test circuit for programmable logic arrays

1981-07-13

1983-10-18

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

044109873

ABSTRACT:
A circuit and a method of operation thereof are disclosed which provides an enhanced test feature for programmable logic arrays. Programmable logic arrays (PLA's) are becoming more complex and many utilize feedback into the array as part of their normal logic function. Those devices utilizing feedback require an abnormally large number of logic cycles to be run in order to provide a known feedback input into the output circuitry so that the combination of all input signals into the array is known. The preload circuit disclosed herein provides a method of applying a known signal to the feedback circuitry, thereby reducing the number of cycles required to complete a test function as well as reducing the number of pins required for the test feature. The circuit is readily fabricated in an integrated circuit form in conjunction with the PLA circuitry. The test circuitry is readily adapted to high speed automated test equipment.

REFERENCES:
patent: 3789205 (1974-01-01), James
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4363124 (1982-12-01), Aichelmann, Jr.

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