Prefix sum pass to linearize A-buffer storage

Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension

Reexamination Certificate

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C345S501000, C345S530000, C345S543000, C345S581000, C712S030000, C707S752000, C707S753000

Reexamination Certificate

active

08081181

ABSTRACT:
The architecture implements A-buffer in hardware by extending hardware to efficiently store a variable amount of data for each pixel. In operation, a prepass is performed to generate the counts of the fragments per pixel in a count buffer, followed by a prefix sum pass on the generated count buffer to calculate locations in a fragment buffer in which to store all the fragments linearly. An index is generated for a given pixel in the prefix sum pass and stored in a location buffer. Access to the pixel fragments is then accomplished using the index. Linear storage of the data allows for a fast rendering pass that stores all the fragments to a memory buffer without needing to look at the contents of the fragments. This is then followed by a resolve pass on the fragment buffer to generate the final image.

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