Prefetch/prestore mechanism for peripheral controllers with shar

Details Prefetch/prestore mechanism for peripheral controllers with shar Prefetch/prestore mechanism for peripheral controllers with shar

1992-10-20

1996-09-17

Lall, Parshotam S.

Boots, shoes, and leggings

364DIGI, 364DIGII, G06F 506

Patent

active

055577504

ABSTRACT:
A single chip peripheral bus adapter circuit has a pair of input and output first in, first out (FIFO) buffers, a main buffer, and a pair of supporting registers. The registers increase the performance of the circuit by eliminating or reducing wait states.

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