Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
2000-05-10
2001-11-20
Niebling, John F. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
C711S119000, C711S113000
Reexamination Certificate
active
06321326
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of microprocessors and, more specifically, to prefetching and caching within microprocessors.
2. Description of the Related Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. On the other hand, superpipelined microprocessor designs divide instruction execution into a large number of subtasks which can be performed quickly, and assign pipeline stages to each subtask. By overlapping the execution of many instructions within the pipeline, superpipelined microprocessors attempt to achieve high performance.
Superscalar microprocessors demand low memory latency due to the number of instructions attempting concurrent execution and due to the increasing clock frequency (i.e. shortening clock cycle) employed by the superscalar microprocessors. Many of the instructions include memory operations to fetch (read) and update (write) memory operands. The memory operands must be fetched from or conveyed to memory, and each instruction must originally be fetched from memory as well. Similarly, superpipelined microprocessors demand low memory latency because of the high clock frequency employed by these microprocessors and the attempt to begin execution of a new instruction each clock cycle. It is noted that a given microprocessor design may employ both superscalar and superpipelined techniques in an attempt to achieve the highest possible performance characteristics.
Microprocessors are often configured into computer systems which have a relatively large, relatively slow main memory. Typically, multiple dynamic random access memory (DRAM) modules comprise the main memory system. The large main memory provides storage for a large number of instructions and/or a large amount of data for use by the microprocessor, providing faster access to the instructions and/or data than may be achieved from a disk storage, for example. However, the access times of modem DRAMs are significantly longer than the clock cycle length of modem microprocessors. The memory access time for each set of bytes being transferred to the microprocessor is therefore long. Accordingly, the main memory system is not a low latency system. Microprocessor performance may suffer due to high memory latency.
In order to allow low latency memory access (thereby increasing the instruction execution efficiency and ultimately microprocessor performance), computer systems typically employ one or more caches to store the most recently accessed data and instructions. Additionally, the microprocessor may employ caches internally. A relatively small number of clock cycles may be required to access data stored in a cache, as opposed to a relatively larger number of clock cycles required to access the main memory.
Low memory latency may be achieved in a computer system if the cache hit rates of the caches employed therein are high. An access is a hit in a cache if the requested data is present within the cache when the access is attempted. On the other hand, an access is a miss in a cache if the requested data is absent from the cache when the access is attempted. Cache hits are provided to the microprocessor in a small number of clock cycles, allowing subsequent accesses to occur more quickly as well and thereby decreasing the effective memory latency. Cache misses require the access to receive data from the main memory, thereby increasing the effective memory latency.
In many applications, different types of data (e.g. constants, execution results, etc.) are used in different ways. For example, constants are read-only and are useful early in the execution pipeline of a microprocessor (e.g. for generating addresses of operands or for the early calculation of intermediate or final execution results involving constants). On the other hand, result data may be write-only (i.e. the results are generated and stored to memory but not used in imminent program execution). Performance of the microprocessor is in many cases unaffected by the point in the execution pipeline at which a result is updated to memory, because often times the result is not immediately needed again. Other data is read/write, in which the values are modified and the modified values subsequently used. A method for decreasing latency to each type of data based upon access mode, is desired.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a microprocessor in accordance with the present invention. The microprocessor described herein is configured to execute a prefetch instruction. The prefetch instruction specifies a cache line to be transferred into the microprocessor, as well as an access mode for the cache line. Furthermore, the microprocessor includes caches optimized for the access modes. The specified cache line is prefetched into the corresponding cache, and is available for optimized access. Advantageously, the prefetched cache lines may be rapidly available to the functional units which access the prefetched cache lines using the access mode specified within the prefetch instruction. Effective memory latency may be decreased due to the reduced latency experienced upon access to the prefetched cache lines. Microprocessor performance may be correspondingly increased.
In one embodiment, the microprocessor includes functional units configured to operate upon various data types. Each different type of functional unit may be connected to different caches which are optimized for the various access modes. The prefetch instruction may include a functional unit specification in addition to the access mode. In this manner, data of a particular type may be prefetched into a cache local to a particular functional unit. Access time to the local caches may be further decreased by the physical location of the caches near the functional unit which accesses those caches. Effective memory latency may be further decreased by prefetching data having a particular data type and access mode into a cache optimized for the access mode and connected to a functional unit configured operate upon that data type.
Broadly speaking, the present invention contemplates a microprocessor comprising a plurality of functional units configured to execute instructions including a prefetch instruction. The prefetch instruction includes a functional unit field identifying one of the plurality of functional units. The identified functional unit is to operate upon data identified by the prefetch instruction. Additionally, the prefetch instruction includes a read/write specifier field indicating an access mode for the data. The microprocessor is configured to prefetch the data in response to the prefetch instruction.
The present invention further contemplates a method for prefetching data in a microprocessor. A prefetch instruction identifying a cache line is executed. The prefetch instruction includes an r/w specifier indicating an access mode for the cache line. Responsive to executing the prefetch instruction, the cache line is fetched into the microprocessor. The cache line is stored in a read-only cache if the access mode is read-only. The read-only cache provides read access to the cache line in response to a load memory operation and inhibits write access to the cache line in response to a store memory operation. If the access mode is write-only, the cache line is stored in a write-only cache. The write-only cache provides write access to the cache line in response to a store memory operation and inhibits read access to the cache line in response to a load memory operation. If the access mode is read/write, the cache line is stored in a read/write cache. The read/write cache provides both read access and write access to the cache line in response to a load memory operation and a store memory operation, respectively.
REFERENCES:
patent: 5317716 (1994-05-01), Liu
patent: 5510934 (1996-04-01), Brennan et al.
patent: 5551001 (1996-08-01), Cohen et al.
patent: 55
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Merkel Lawrence J.
Niebling John F.
Whitmore Stacy
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