Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
1998-12-04
2001-01-09
Treat, William M. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
C711S213000, C711S217000, C711S218000
Reexamination Certificate
active
06173392
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a prefetch controller and more particularly to a prefetch controller which detects a regularity of addresses of data to be accessed sequentially and then prefetches data.
A conventional cache memory controller transfers data from a storage unit to cache memory when required data is not found in the cache memory (hereafter, this condition is called a cache miss). Further, as a software-controlled method, cache data prefetch instructions specify data to be transferred from a storage unit to cache memory in advance.
However, because the cache memory controller starts accessing the storage unit upon detection of a cache miss, it takes some time for the central processing unit to receive data and therefore cannot continue execution of an instruction requiring the data. Another problem is that a cache miss, if generated on a recent central processing unit having a pipeline installed for higher throughput, sometimes stops the pipeline, degrading the performance of the central processing unit.
In the software-controlled method, cache data prefetch instructions explicitly specifying prefetch operations in a program increase the program size, degrading performance. Another problem with this method is that it is usually impossible to predict correctly where access to the storage unit will be made within the program and, therefore, it is difficult to generate prefetch instructions at correct locations within the program at compilation time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a prefetch controller which predicts access that will be made by the processor to consecutive addresses at a fixed interval and prefetches required data into cache memory in advance to increase system performance.
In one preferred embodiment, the prefetch controller according to the present invention has a history of request addresses issued from the processor to the cache memory and the difference between each request address and the previous request address. If the difference between the current request address and one of the request addresses in the history matches the difference corresponding to that request address in the history, the prefetch controller adds the address difference to the current request address to generate a prefetch address and issues a prefetch request specifying that prefetch address.
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Japanese Office Action dated Jan. 25, 2000 with partial translation.
Shinozaki Mayumi
Shinozaki Takashi
Benson Walter
McGinn & Gibb, P.C.
NEC Corporation
Shinozaki Mayumi
Treat William M.
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