Prefetch circuit for a computer memory subject to consecutive ad

Details Prefetch circuit for a computer memory subject to consecutive ad Prefetch circuit for a computer memory subject to consecutive ad

1987-12-11

1990-04-17

Shaw, Gareth D.

Boots, shoes, and leggings

3642631, 3642464, 364243, 3649663, 36496433, G06F 1200

Patent

active

049185870

ABSTRACT:
A computer memory prefetch architecture for accelerating the rate at which data can be accessed from memory and transmitted to a processor when successive addresses are numerically consecutive. Upon the identification of a consecutive address sequence, the succession of real addresses are generated directly by a counter. The memory of the computer system is partitioned into odd and even banks which are selectively addressed using the odd and even segments of the address generated in the counter. Output data from each memory bank is stored in a corresponding register operable to transmit the data entered therein during a previous memory address cycle while the anticipated next address data is written into the other register. The prefetch architecture may be meaningfully used to accelerate the access rate of a memory shared by multiple processors.

REFERENCES:
patent: 3931613 (1976-01-01), Gruner et al.
patent: 4095265 (1978-06-01), Vrba
patent: 4424561 (1984-01-01), Stanley et al.
patent: 4583162 (1986-04-01), Prill
patent: 4621320 (1986-11-01), Holste et al.
patent: 4652993 (1987-03-01), Scheumeman et al.
patent: 4661900 (1987-04-01), Chen et al.
IBM Technical Disclosure Bulletin, vol. 26, No. 7B, Dec. 1983, pp. 3941-3944.

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