Prefetch architectures for data and time signals in an...

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1999-10-22

2003-03-04

Chin, Stephen (Department: 2734)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S154000, C327S288000, C327S294000, C327S394000, C375S354000, C375S377000

Reexamination Certificate

active

06529054

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to circuits for synchronizing data capture in an integrated circuit. More particular, the present invention relates to circuits for synchronizing data capture and outputting the captured data at a significantly higher frequency than the frequency of the individual data lines and/or utilizes reduced voltage signals to reduce power consumption and to increase performance.
In any integrated circuit (IC), data signals often need to be transmitted from one circuit at one location on the IC to a receiving circuit at another location on the IC. As is well known by those skilled in the art, the data contained in the data signal is present in well defined data cycles, each of which has a finite period during which the data is valid for capture. Given that a data cycle is valid only for a limited period of time, it is crucial to ensure that the receiving circuit captures data during this relatively short period of time. This is particularly true in modern high speed IC's, which vastly reduce the duration of the data valid period, i.e., the time period during which data capturing must be performed.
To address the problem of properly capturing data at the receiving circuit during the limited time during which the data cycle is valid, timing or clock signals may be furnished to the receiving circuit. The use of a synchronized data capture circuit to synchronize data capture at the receiving circuit is well known. In general, if the timing signal tracks the data signal properly, the receiving circuit can depend on the timing information furnished in the timing signal to decide when to capture the data contained in the data signal.
To facilitate discussion,
FIG. 1A
illustrates a prior art circuit
100
for synchronizing data capture at a receiving circuit on the IC. Circuit
100
as shown includes a timing delay/driver
102
, a data delay/driver
104
, and a clocked data driver
106
. A data signal
108
as shown at the input of the data delay/driver
104
, which is clocked by a control signal
110
, to produce a clocked data signal
112
. The same control signal
110
also clocks timing delay/driver
102
, producing a timing signal
114
. Timing delay/driver
102
and data delay/driver
104
ensure that timing signal
114
properly tracks clocked data signal
112
for the specific IC on which circuit
100
is implemented to allow clocked data driver
106
to properly capture the data contained in clocked data signal
112
based on the timing information furnished by timing signal
114
. The captured data as shown is outputted from clocked data driver
106
as output data
116
in FIG.
1
A. The data synchronizing circuit of
FIG. 1A
is well known and will not be belabored further for the sake of brevity.
Although circuit
100
of
FIG. 1A
accomplishes the function of synchronizing data capture, there are significant disadvantages. By way of example, prior art data synchronizing circuit
100
generally synchronizes data capture at the speed of data transmission on the individual data lines (e.g., individual ones of data lines
108
). In other words, data is captured and outputted from prior art data synchronizing circuit
100
of
FIG. 1A
at the relatively slow speed of data transmission on data lines
108
. The speed of data transmission on data lines
108
is generally slow due to a couple of factors. For example, data on each individual data line
108
is typically obtained by reading from the array of storage cells, which operate at a relatively slow frequency compared to the frequency of the logic circuits which request the data from the memory array. Further, a given data line
108
in a typical dynamic random access memory circuit is typically long and heavily loaded, thereby severely limiting the speed at which data may be transmitted on an individual data line. Accordingly, unless the data synchronizing circuit is capable of capturing and outputting the data at a higher speed (i.e., substantially higher than the speed at which data is transmitted on individual data lines
108
), device performance suffers due to the bottleneck between the higher speed logic circuits that request the stored data and the slower dynamic random access memory circuits that supply the data stored.
Another major disadvantage of the configuration shown in
FIG. 1A
relates to the fact prior art circuit
100
needs to operate with full swing signals (i.e., signals having the full rail-to-rail internal supply voltage swing of the IC) to perform synchronized data capture. More specifically, prior art circuit
100
is incapable of utilizing reduced voltage signals to perform the synchronized data capture task. As the term is employed herein, reduced voltage signals refer to signals whose amplitude is within a reduced voltage range, i.e., a voltage range that is lower than the full VDD internal supply voltage of the IC. In some cases, the reduced voltage level may be low enough (e.g., 1V) that it approaches the threshold voltage of the transistors (typically at around 0.7V or so). Since reduced voltage signals are useful in reducing circuit power consumption and/or improving performance, the inability of prior art circuit
100
to employ reduced voltage signals to perform its synchronized data capture task represents a serious shortcoming.
One reason underlying the inability of prior art circuit
100
to employ reduced voltage signals to perform synchronized data capture relates to one of its basic building block, the CMOS inverter. CMOS inverters are a basic building block of delay circuits, such as those present in timing/delay driver
102
and data delay/driver
104
. To facilitate discussion,
FIG. 1B
depicts a simple CMOS inverter
150
, which includes a p-FET transistor
152
coupled in series with an n-FET transistor
154
between VDD and ground.
Consider first the situation wherein a full swing signal is employed at the input of CMOS inverter
150
: When input signal A at the input of CMOS inverter
150
is high at the VDD level, p-FET
152
is off and n-FET
154
is on, causing output signal B to be pulled to ground. Conversely, when input signal A at the input of CMOS inverter
150
is low at the ground level, p-FET
152
is on and n-FET
154
is off, causing output signal B to be pulled to VDD. In this case, CMOS inverter
150
functions correctly, albeit at a relatively high level of power consumption.
Now consider the situation wherein a reduced voltage signal is employed as an input signal A to CMOS inverter
150
. If the reduced voltage signal is, for example, 1 Volt, a high input signal A not only causes n-FET
154
to be on as expected but also causes p-FET
152
to be softly on (i.e., not fully turning p-FET
152
off). In this case, the leakage current through p-PET
152
degrades the signal at the output of CMOS inverter
150
, which may cause other circuits to misinterpret the logic level represented by output signal B of CMOS inverter
150
. Furthermore, the leakage current through p-PET
152
to ground also causes CMOS inverter
150
to consume an unacceptable amount of power. Because of these issues and others, reduced voltage signals have not, to date, been employed in synchronized data capturing circuits to perform the synchronized data capture task.
As can be appreciated from the foregoing, there are desired synchronized data capturing circuits and methods therefore that can synchronize data capture at a substantially higher frequency than the frequency of the individual data lines and/or utilize reduced voltage signals to reduce power consumption and to increase performance.
SUMMARY OF THE INVENTION
The invention relates, in one embodiment, to a synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing

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