Preemption control for central processor with cache

Details Preemption control for central processor with cache Preemption control for central processor with cache

1989-10-27

1994-03-08

MacDonald, Allen R.

Boots, shoes, and leggings

364229, 3642301, 3642304, 364240, 3642404, 3642434, 3642426, 36424292, 36424341, 3642513, 364260, 364270, G06F 1300

Patent

active

052934934

ABSTRACT:
A logic controlled gate is inserted in the arbitration logic of a computer system that supports multiple masters on a data bus. In such a system with arbitration for data bus ownership, the gate is so controlled that competitors for the data bus cannot force the main processor (CPU) from the data bus until certain system conditions are met. In particular, a pattern of CPU "hits" to memory cache is recognized as an opportunity for the CPU to relinquish the data bus.

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IBM Technical Disclosure Bulletin, vol. 32, No. 10A, dated Mar. of 1990, pp. 50-54.

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