Predictive snooping of cache memory for master-initiated accesse

Details Predictive snooping of cache memory for master-initiated accesse Predictive snooping of cache memory for master-initiated accesse

1995-07-07

1998-01-20

Chan, Eddie P.

395468, G06F 1328, G06F 1208

Patent

active

057109060

ABSTRACT:
When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.

REFERENCES:
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5535363 (1996-07-01), Prince
PCI Special Interest Group, "PCI Local Bus Specification-Production Version" (Apr. 30, 1993), Rev. 2.0.
Intel Corporation, "82433LX/82433NX Local bus Accelerator (LBX)", Advance Information (Apr. 1994), pp. 13-15.
Intel Corporation, "82434LX/82434NX PCI, Cache and Memory Controller (PCMC)", Advance Information (Mar. 1994), pp. 96-103, 152-154.
Intel Corporation, "Pentium.TM. Processor User's Manua--vol. 1: Pentium Processor Data Book" (1993).

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