Predictive clock recovery circuit

Details Predictive clock recovery circuit Predictive clock recovery circuit

1988-10-03

1990-07-10

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375110, 3281301, H04L 7033

Patent

active

049411519

ABSTRACT:
A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive previous transitions. A phase locked oscillator which is driven by said SPL pulse generates the extracted clock signal which is in phase with the SPL pulse and coincides with the center of the eye intervals of said multilevel digital signal. The system includes a first counter N which starts running in response to the detection of the first transition of the multilevel digital signal. The running stops when the second transition occurs. The result N(i) stored into the first counter N at second transition is therefore representative of the duration between the two consecutive first and second transitions. The preferred embodiment of the invention also involves an up/down counter K which generates a second counter K(i) that is expected to be representative of half the value of the first counter N(i). Counter K is adaptively updated by incrementing its current value K(i) by a fixed factor or, on the contrary, by decrementing its current value K(i) by a fixed damping factor.

REFERENCES:
patent: 3633108 (1972-01-01), Kneuer
patent: 4029905 (1977-06-01), Abraham
patent: 4267595 (1981-05-01), Hernandez
patent: 4423518 (1983-12-01), Hirosaki
patent: 4599735 (1986-07-01), Surie et al.
patent: 4799239 (1989-01-01), Pearlman et al.

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