Predictive addressing architecture

Details Predictive addressing architecture Predictive addressing architecture

1994-07-22

1996-01-16

Whitfield, Michael A.

Boots, shoes, and leggings

395375, 364DIG1, G06F 1202, G06F 1300

Patent

active

054855896

ABSTRACT:
A computer system where memory access is accelerated by automatically incrementing the address at the memory chip inputs, as soon as the minimum hold time has occurred. If the next address actually requested by the CPU does not match this predicted address, then the actual address is driven onto the chip inputs as usual, so essentially no time is lost. However, if the automatically incremented address does match the next actually requested address, then a significant fraction of the chip's required access time has been saved.

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