Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2008-07-07
2011-12-27
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S014000, C703S022000, C703S024000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
08086429
ABSTRACT:
A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist.
REFERENCES:
patent: 5491640 (1996-02-01), Sharma et al.
patent: 5544071 (1996-08-01), Keren et al.
patent: 5659555 (1997-08-01), Lee et al.
patent: 6035109 (2000-03-01), Ashar et al.
patent: 6086626 (2000-07-01), Jain et al.
patent: 6163876 (2000-12-01), Ashar et al.
patent: 6301687 (2001-10-01), Jain et al.
patent: 6385765 (2002-05-01), Cleaveland et al.
patent: 6587998 (2003-07-01), Rodeh
patent: 6711730 (2004-03-01), Frank et al.
patent: 6816825 (2004-11-01), Ashar et al.
patent: 6874135 (2005-03-01), Gupta et al.
patent: 6944838 (2005-09-01), McMillan
patent: 7065726 (2006-06-01), Singhal et al.
patent: 7117463 (2006-10-01), Graham et al.
patent: 7149987 (2006-12-01), Zhu et al.
patent: 7159198 (2007-01-01), Ip et al.
patent: 7299432 (2007-11-01), Baumgartner et al.
patent: 7337100 (2008-02-01), Hutton et al.
patent: 7356792 (2008-04-01), Baumgartner et al.
patent: 7370298 (2008-05-01), Baumgartner et al.
patent: 7380222 (2008-05-01), Baumgartner et al.
patent: 7437690 (2008-10-01), Baumgartner et al.
patent: 7653884 (2010-01-01), Furnish et al.
patent: 7921393 (2011-04-01), Furnish et al.
patent: 2003/0208730 (2003-11-01), Singhal et al.
patent: 2005/0114809 (2005-05-01), Lu
patent: 2005/0198597 (2005-09-01), Zhu et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2008/0134115 (2008-06-01), Ly et al.
patent: 2008/0270086 (2008-10-01), Baumgartner et al.
Baumgartner et al., U.S. Appl. No. 11/249,937, Office Action dated Jan. 28, 2008.
Baumgartner et al., U.S. Appl. No. 11/333,606, Office Action dated Mar. 5, 2009.
Baumgartner et al., U.S. Appl. No. 12/129,976, Office Action dated Jun. 9, 2011.
Baumgartner et al., U.S. Appl. No. 12/129,976, Notice of Allowance dated Oct. 25, 2010.
Zaraket et al., “Scalable Composotional minimization via Static analysis”, International Conference on Computer Aided Design—Proceedings of the 2005 IEEE/ACM International Conference, 06-10, Nov. 2005 (pp. 1057-1067).
Baumgartner et al., “An Abstraction Algorithm for verification of Level-Sensitve Latch-Based Netlists”—Proceedings of the Conference on Computer-Aided Verification, Jul. 1999 (pp. 1-26) (Formal Methods in System Design 2003—Springer).
Alpert et al., Multilevel Circuit Partitioning, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Aug. 1998, vol. 17, No. 8, pp. 655-667.
Ford Jr et al., Maximal Flow Through a Network, Canadian Journal of Mathematics, 1956, vol. 8, No. 3, pp. 399-404.
Kuehlmann et al., Transformation-Based Verification Using Generalized Retiming, Computer Aided Verification, Jul. 2001, pp. 104-117.
Dong Wang & Jeremy Levitt, “Automatic assume guarantee analysis for assertion-based formal verification”—ASP-DAC 2005, IEEE (pp. 561-566).
Miroslav N. Velev, “Exploiting signal unobservability for efficient translation to CNF in formal verification of microprocessors”—Proceedings of the design, automation and test in Europe conference and exhibition (DATE'04) Mar. 8, 2004, IEEE (pp. 1-6).
Tiziana Margaria, “Fully automatic verification and error detection for parameterized iterative sequential circuits”, Computer Science, 1996, vol. 1055/1996 (pp. 258-277).
Baumgartner Jason R.
Mony Hari
Paruthi Viresh
Zaraket Fadi A.
International Business Machines - Corporation
Phan Thai
Yudell Isidore Ng Russell PLLC
LandOfFree
Predicate-based compositional minimization in a verification... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Predicate-based compositional minimization in a verification..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Predicate-based compositional minimization in a verification... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4306486