Predecoding instructions for supercalar dependency indicating si

Details Predecoding instructions for supercalar dependency indicating si Predecoding instructions for supercalar dependency indicating si

1992-12-04

1994-08-09

Harrell, Robert B.

Boots, shoes, and leggings

395500, 3643319, 3642287, 3642554, 3642625, 364263, 36493142, 36493103, 3649378, 3649428, 3649463, 3649483, G06F 930, G06F 938

Patent

active

053374150

ABSTRACT:
A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilization by a superscalar processor. The circuitry of the predecode unit is comprised of logic and latches. The predecode unit includes two main paths for transporting instruction information: a predecode path and an instruction path. The instruction path buffers instructions sent from memory to cache as information from these instructions are decoded in the predecode path. The predecode path includes a decoder and a bit information unit. The decoder identifies the instruction type by monitoring the op-code of instructions entering the predecode unit. The bit information unit is coupled to the decoder and receives signals indicating instruction type and passes these signals through logic gates to obtain whether instructions can be bundled. The bit information unit then transfers to cache bundle signals and instruction type signals. These signals are stored as predecode bits along with instructions from the instruction path in the cache.

REFERENCES:
patent: 4439828 (1984-03-01), Martin
patent: 4722050 (1988-01-01), Lee et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5197135 (1993-03-01), Eickemeyer et al.
patent: 5214763 (1993-05-01), Blaner et al.

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