Predecode and multiplex in addressing electrically programmable

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307468, 307581, 307449, 365230, 341102, H03K 17687

Patent

active

048189006

ABSTRACT:
An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. The number of transistors needed in the decoder for the row select function is greatly reduced by employing predecoders which perform a 1-of-4 select for each pair of address bits, then using one of these select outputs to activate N multiplexers, and all the others as inputs to a decoder with N outputs to the multiplexers.

REFERENCES:
patent: 3381270 (1968-04-01), Huffman
patent: 3440646 (1969-04-01), Dean
patent: 3539823 (1970-11-01), Zuk
patent: 3851186 (1974-11-01), Koo
patent: 4104735 (1978-08-01), Hofmann
patent: 4143359 (1979-03-01), Beelitz

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