Preconditioning of source data for packed min/max instructions

Details Preconditioning of source data for packed min/max instructions Preconditioning of source data for packed min/max instructions

1999-12-22

2003-03-25

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S671000

Reexamination Certificate

active

06539408

ABSTRACT:

FIELD OF THE INVENTION
Embodiments of the present invention relate to preconditioning of source data for a packed min/max instructions of a processor.
BACKGROUND OF THE INVENTION
Known methods and apparatus can perform a minimum/maximum operation (a min/max operation), i.e., can compare a pair of source data and output either the source data that is the maximum of the pair of source data (a max operation) or the source data that is the minimum of the pair of source data (a min operation).
FIG. 1
shows a known apparatus that can perform a known min/max operation on a pair of data, e.g., S
2
and S
1
. An adder
101
and invertor
111
can subtract S
1
from S
2
when C
1
in is a logical one (e.g., adder
101
and invertor
111
perform twos-complement subtraction). The adder
101
outputs a carry, C
1
[
15
], that can indicate whether S
2
is greater than S
1
. If S
2
is less than S
1
, then C
1
[
15
] will be zero and multiplexer (mux)
106
will select S
2
as the min output. If S
1
is less than S
2
, then C
1
[
15
] will be one and mux
106
will select S
1
as the min output.
A second set of logic circuits can be used to perform a max operation on S
2
and S
1
, the second set of logic including adder
102
, inverter
112
, and mux
107
. Adder
102
and invertor
112
can subtract S
1
from S
2
when C
2
in is a logical one (e.g., adder
102
and invertor
112
perform twos-complement subtraction). The adder
102
outputs a carry, C
2
[
15
], that can indicate whether S
2
is greater than S
1
. If S
2
is greater than S
1
, then C
2
[
15
] will be one and mux
107
will select S
2
as the max output. If S
1
is greater than S
2
, then C
2
[
15
] will be zero and mux
107
will select S
1
as the max output.
One type of min/max operation is a Packed min/Packed max operation, which can be executed by a processor that executes SIMD (single instruction, multiple data) instructions. A SIMD instruction can include packed source data, e.g., eight bytes of source data, four words of source data, four signed words of source data, etc. A Packed min /Packed max (Pmin/Pmax) instruction can be executed by the processor to enhance video processing, audio processing, etc. Examples of uses of Pmin/Pmax operations include analyzing video pixel data (e.g., determining which pixel is darker, etc.) as part of morphing video images, overlaying video images, etc. Video pixel data can be encoded using signed word data (e.g., 16 bit data having a positive or negative value). Audio processing applications can also utilize Pmin/Pmax operations, such as analyzing audio data to determine differences in audio volumes. Audio data can be encoded using unsigned byte data (e.g., 8 bit data that is unsigned). Implementation of Pmin/Pmax operations in hardware can require additional hardware logic.
Known min/max operations can require two sets of logic circuits, including two adders. Additional logic can disadvantageously consume silicon area resources of a processor, an integrated circuit, etc. In view of the foregoing, it can be appreciated that a substantial need exists for methods and apparatus which can advantageously perform min/max operations.
SUMMARY OF THE INVENTION
Embodiments of the present invention include apparatus and methods to precondition source data for packed minimum/maximum operations. A first selector can be coupled to a first invertor and a first input, and a second selector can be coupled to a second invertor and a second input. An adder can be coupled to said first selector and said second selector. A third selector can be coupled to said adder, the first input, and the second input.


REFERENCES:
patent: 5515306 (1996-05-01), Blaner
patent: 5726923 (1998-03-01), Okumura et al.
patent: 5894426 (1999-04-01), Ju
patent: 6341296 (2002-01-01), Menon

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