Precision timing control programmable logic device

Details Precision timing control programmable logic device Precision timing control programmable logic device

1992-06-11

1993-08-24

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307443, 307603, 307606, 307590, H03K 506

Patent

active

052392139

ABSTRACT:
A programmable logic device is disclosed having a delay line macrocell with programmably selectable taps feeding inputs to a programmable logic circuit. The delay line taps may feed the programmable logic circuit through logic circuit driving circuitry, which performs a certain amount of prepossessing on the tap signals before being provided to the programmable logic circuit. Outputs of the programmable logic circuit, which may be a programmable AND array followed by a fixed OR array, are provided to the edge-triggered inputs of dual set/reset flip flops. Other outputs of the programmable logic circuit are selectable as inputs to the delay line.

REFERENCES:
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patent: 4513427 (1985-04-01), Borriello et al.
patent: 4623805 (1986-11-01), Flora et al.
patent: 4745310 (1988-05-01), Swapp
patent: 4845390 (1989-07-01), Chan
patent: 4967110 (1990-10-01), Matsuura
patent: 4975605 (1990-12-01), Bazes
patent: 4994695 (1991-01-01), Bazes

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