Precision rounding in a floating point arithmetic unit

Details Precision rounding in a floating point arithmetic unit Precision rounding in a floating point arithmetic unit

1986-06-02

1988-07-19

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

047589728

ABSTRACT:
A floating point computation unit having an arithmetic unit employing two guard digits for preserving information needed for rounding and an indicator generator for providing an indicator signal to a precision rounding apparatus. The indicator generator detects any digits beyond the guard digits of a shifted operand instead of waiting to detect such digits in the mantissa produced by an add or subtract cycle. The indicator generator comprises a priority encoder network coupled to a comparator for determining whether or not the least significant digits beyond the guard digits of the shifted mantissa are all zeros.

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IEEE Computer Society Computer Standards Committee, "A Proposed Standard for Binary Floating-Point Arithmetic", Draft 10.0 of IEEE Task P754, Dec. 2, 1982.

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