Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-07-20
2002-11-26
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185280
Reexamination Certificate
active
06487116
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor memories and, in particular, to the programming of nonvolatile semiconductor memories.
BACKGROUND OF THE INVENTION
Nonvolatile semiconductor memory integrated circuits, such as EEPROM, EPROM, and FLASH, have traditionally been used to store a single digital bit per memory cell, which is termed hereafter as single bit storage. Memories capable of storing more than one bit of digital data per memory cell and their benefits have been described previously and are called multilevel memories. A level represents a specific range of electrical charge stored in each memory cell. To store N bits per memory cell requires 2
N
discrete levels. Each discrete level corresponds to a unique binary data pattern for all N bits. The cell is erased or programmed to store charge within one of these 2
N
discrete levels. Sensing circuits determine which level of charge is stored in the cell and read out the corresponding binary data pattern stored for the N bits. Digital information can thus be stored at a significantly lower cost per bit since N times the number of bits can be stored in the same memory cell array area previously storing just a single bit per cell.
Nonvolatile semiconductor memory integrated circuits using EEPROM and FLASH memory cells have also been used to store analog information. In this case, the amount of electrical charge stored in each memory cell is part of a continuum instead of discrete multiple levels. The precision of the stored charge determines the signal-to-noise ratio of the analog information.
EEPROM, EPROM, and FLASH memory cells are typically based on silicon gate MOS transistor technology. Such a nonvolatile memory cell
100
is shown in FIG.
1
. Charge is stored on a piece of silicon which is called a floating gate
105
. This gate is completely surrounded by silicon dioxide which, ideally, can only pass charge during program or erase operations and so is called “floating”. The floating gate
105
is formed near a silicon channel
110
between a source
115
and a drain
120
diffusion regions. The floating gate
105
voltage is determined by the amount of charge stored and by the adjacent capacitive coupling to a control gate
125
, source
115
, drain
120
, and channel
110
. The conductivity of the silicon channel
110
is controlled by the floating gate
105
voltage in an similar manner as in a classic MOS transistor.
Nonvolatile memory cell programming requires charge passage through an oxide
130
to the floating gate
105
and is accomplished via two mechanisms; tunneling and hot carrier injection. Hot carriers, in the case of an n-channel device, are electrons with sufficient energy to conduct through silicon dioxide. Hot electron programming requires two basic conditions to be met. First, a source of hot electrons must be generated in the channel
110
. This is accomplished by creating a high electric field region, Eh
135
, in the channel
110
to accelerate the electrons to an energy sufficient to make them “hot”. In
FIG. 1
the flow of electrons in the channel
110
is represented by a source current, Is
140
, and a drain current, Id
145
. Second, a vertical electric field, Ev
150
, between the floating gate
105
and channel
110
must attract the hot electrons toward the floating gate
105
. The hot electrons which flow to the floating gate
105
create a floating gate charging current, Ig
155
.
Many different cell structures exist utilizing the hot carrier injection mechanism; all require the two basic conditions described above.
FIGS. 2A-2D
show some examples of such cells. In a Channel Hot Electron injection (CHEI) cell design
200
A, the cell is biased in a saturated mode of transistor operation. A high electric field region, Eh
235
A, is generated between a drain
220
A and a point of channel saturation
260
A. More recently, cells have been designed which generate a high Eh
235
B and
235
C midway in the channel by extending a control gate
225
B and
225
C over a channel
210
B and
210
C on a source end
215
B and
215
C of a cell
200
B or with an additional gate
270
C as shown in a High Efficiency Source Side Channel Hot Electron Injection (HESSCHEI) cell
200
C. A high Eh
235
D can also be generated near a source
215
D by a Source Side injection (SSI) cell
200
D.
There are many technical challenges associated with multilevel and analog nonvolatile memories. Since the total charge storage range for a cell is constrained, the amount of charge stored in the memory cell must be controlled within a very narrow range for each level in a multilevel memory. The severity of this problem increases geometrically as the number of bits stored per multilevel memory cell increases since 2
N
discrete levels per cell are required to store N bits per cell. In analog memory the total charge storage range must cover the dynamic range of the analog signal. The precision of the stored charge determines the signal-to-noise ratio of the analog information. For analog signals the challenge is dealing with signals with wide dynamic range and/or high signal-to-noise ratio. In both applications the charge must be initially stored during programming with a high degree of precision.
To obtain the programming precision required for multilevel cells, iterative programming algorithms have been used. These algorithms provide a programming voltage pulse followed by a read or verify step. The program/verify sequence is repeated until the desired charge storage level in the cell is reached with the desired precision. As more charge is stored on the floating gate
105
, the Ev
150
reduces, thereby slowing the programming. To continue programming at a sustained rate, the biasing voltages applied to the control gate
125
or drain
120
are increased with subsequent programming pulses. Hot carrier injection programming methods require high voltages, beyond the power supply voltages, to be applied to the control gate
125
and drain
120
of the cell to generate sufficiently high Eh
135
and Ev
150
. Controlling such high voltages in a complex algorithm increases circuit complexity.
The read or verify sensing steps must be accomplished with adequate precision to halt the programming algorithm at the desired level in the case of multilevel and at the correct charge state for analog storage. Various sensing approaches have been described and can be generally divided into two modes of operation. During current-mode sensing, the current flowing in the cell is dependent on the charge stored in the cell. The cell is biased by applying voltages and a current flowing in the cell is sensed. During voltage-mode sensing, the current flowing in the cell is not dependent on the charge stored in the cell. In voltage-mode, the cell is biased by applying a fixed current and a voltage is sensed which corresponds uniquely to the amount of charge stored on the floating gate of the cell.
Hot carrier injection programming in present technologies takes place quickly in the range of 0.5 to 5 microseconds. This is due to the high programming voltages which generate high cell channel currents Is
140
and Id
145
, some of which is sent towards the floating gate
105
. This fast programming makes it difficult to maintain precision for multilevel and analog applications. The high current poses power problems which may prevent the use of a single power supply voltage for the chip. It also restricts the number of cells which can be simultaneously programmed in a “page” of cells. Methods to reduce the programming current have been proposed at the expense of adding extra processing complexity to the cell.
The present invention solves or substantially mitigates these problems. A memory circuit according to the present invention controls the programming current directly and accomplishes a high degree of programming precision.
SUMMARY OF THE INVENTION
The present invention provides for an integrated circuit memory system and method for the precision programming of single or a plurality of nonvolatile memory cells.
Khan Sakhawat M.
Korsh George J.
Gray Cary Ware & Freidenrich LLP
Ho Hoai
Silicon Storage Technology, Inc.
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