Precision low power operational amplifier with gain...

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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C330S260000

Reexamination Certificate

active

06411164

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to communication systems and components, and is particularly directed to a new and improved precision, low power operational amplifier that employs a transconductance amplifier architecture of the type described in my above-referenced '408 application, and is configured to enjoy a wide operational bandwidth at any closed looped gain, while at the same time maintaining DC precision.
BACKGROUND OF THE INVENTION
As described in the above-referenced '408 application, the transmission channels of subscriber line interface circuits, or SLICs, employed by telecommunication service providers include a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low power consumption, low noise, filtering, and ease of impedance matching programmability, to facilitate interfacing the SLIC with a variety of telecommunication circuits including those providing digital codec functionality. In a typical application, the length of the wireline pair to which a SLIC is connected can be expected to vary from installation to installation, may have a significant length (e.g., on the order of multiple miles), and is used to transport both substantial DC voltages, as well as AC signals (e.g., voice and/or ringing). As a consequence, it has been difficult to realize a SLIC implementation that has ‘universal’ use in both legacy and state of the art installations.
In accordance with the invention disclosed in the above-referenced '408 application, such shortcomings of conventional transconductance amplifier circuits are effectively obviated by a new and improved transconductance amplifier circuit architecture, a schematic diagram of a non-limiting bipolar transitor-based implementation of which is shown in
FIG. 1
, and which is configured to transform a single ended input voltage into a very precise, single ended output current, without requiring a substantial quiescent current, and in a manner which is effectively independent of (differential) voltage supply rails through which the circuit is powered.
In
FIG. 1
, the transconductance amplifier circuit is shown as including an operational amplifier configured as a unity gain buffer
100
. The operational amplifier has a dual polarity input operational amplifier input and gain stage
110
, and a low output impedance, single ended output stage
120
. The input and gain stage
110
, which may have a conventional high impedance, moderate voltage gain circuit configuration, has a first, non-inverting polarity input
111
, that is adapted to be coupled to a DC reference voltage, shown as a voltage v
0
(relative to ground (GND)) , and a second, inverting polarity input
112
, which is adapted to track the voltage v
0
. The input voltage v
0
can be selected in compliance with the overhead voltages and power dissipation required by the specific application in which the transconductance amplifier circuit is employed.
The output stage
120
includes a differentially coupled transistor circuit pair, having a first, diode-connected NPN transistor
130
, whose collector
131
and base
132
are connected in common to a first polarity output port
113
of the amplifier's input stage
110
. The emitter
133
of transistor
130
is coupled in common to the emitter
143
of a second, diode-connected PNP transistor
140
. In a complementary fashion, PNP transistor
140
has its collector
141
and base
142
connected in common to a second polarity output port
114
of the amplifier input stage
110
. The base
132
of NPN transistor
130
is coupled n common with the base
152
of an NPN transistor
150
, the emitter
153
of which is coupled in common to the emitter
163
of a PNP transistor
160
and to an input/output node
123
of output stage
120
.
The PNP transistor
160
has its base
162
coupled in common with the base
142
of the PNP transistor
140
. The output stage has an input/output node
123
coupled in a follower configuration over a negative feedback path
126
to the inverting input
112
of the input stage
110
. Unlike a conventional amplifier circuit, the input/output node
123
, rather than being employed to supply an output current to a downstream load, is coupled to receive one or more input currents, respectively supplied through one or more coupling resistors, to associated voltage feed ports. In order to reduce the complexity of the drawing
FIG. 1
shows a single input-coupling resistor R
1
coupled between node
123
and an input port
125
. With a voltage Vin applied to the input port
125
, a current Iin will flow through input resistor R
1
.
The series-connected, collector-emitter current paths through the output transistors
150
and
160
of the amplifier's output stage
120
, rather than being biased via a direct coupling to respective (Vcc and Vee) voltage supply rails
155
and
156
, are coupled in circuit with first current supply paths
171
and
181
of first and second current mirror circuits
170
and
180
, respectively. These current mirror circuits serve to isolate the biasing of the amplifier's output stage
120
from its power supply terminals, so that the output current produced at a single ended output node/port
135
can be accurately controlled independent of the values of the power supply voltages.
The current mirror circuit
170
includes a first PNP transistor
200
having its emitter
203
coupled to the (Vcc) voltage supply rail
155
, and its base
202
coupled in common with the base
212
and collector
211
of a diode-connected current mirror PNP transistor
210
, the emitter
213
of which is coupled to (Vcc) voltage supply rail
155
. The current mirror transistor
200
supplies a mirrored output current to the current supply path
172
as a prescribed factor K of the current received by transistor
210
over the current supply path
171
, in accordance with the ratio (1:K) of the geometries of the transistors
210
/
200
. The collector
211
and base
212
of transistor
210
are coupled over the first current supply path
171
of the current mirror
170
to the collector
151
of transistor
150
of the output stage
120
. The collector
201
of transistor
200
is coupled over a second current supply path
172
of the current mirror
170
to the transconductance stage's single ended output node/ port
135
.
The current mirror circuit
180
includes a first NPN transistor
220
having its emitter
223
coupled to the (Vee) voltage supply rail
156
and its base
222
coupled in common with the base
232
and collector
231
of a diode-connected current mirror NPN transistor
230
, whose emitter
233
is coupled to (Vee) voltage supply rail
156
. The collector
231
and base
232
of the current mirror transistor
230
are coupled over the first current supply path
181
of the current mirror
180
to the collector
161
of output stage transistor
160
. The collector
221
of transistor
220
is coupled over a second current supply path
182
of the current mirror
180
to the output node
135
. The current mirror transistor
220
provides a mirrored output current to current supply path
182
as a factor K of the current received by transistor
230
over current supply path
181
, in accordance with the (1:K) ratio of the geometries of transistors
230
/
220
.
An examination of current node equations (set forth below), that define the transfer function of the transconductance amplifier circuit of
FIG. 1
, reveals that it has a very wide dynamic range and is capable of accommodating single or multiple, differential polarity voltages applied at its one or more voltage feed ports. This wide dynamic range is obtained at a very low quiescent power dissipation.
More particularly, the single ended output current i
123
delivered to input/output node
123
may be defined in equation (1) as:
i
123
=(
v
125−1
−v
111
)/
R
1
  (1)
The currents i
171
and i
181
supplied to current mirrors
170
and
180
may be related to the

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