Precision high-K intergate dielectric layer

Details Precision high-K intergate dielectric layer Precision high-K intergate dielectric layer

2002-04-08

2004-06-15

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S396000, C438S287000, C438S296000, C438S297000

Reexamination Certificate

active

06750066

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor devices having dielectric layers. In particular, the present invention relates to a precision high-K intergate dielectric layer and a method of forming the same.
BACKGROUND
A conventional floating gate FLASH memory device includes a FLASH memory cell characterized by a vertical stack on a semiconductor substrate. The semiconductor substrate is doped with either n-type or p-type impurities to form an active region in the semiconductor substrate. The vertical stack includes a gate dielectric, a floating gate, an intergate dielectric layer and a control gate. The gate dielectric of silicon dioxide (SiO
2
gate dielectric), for example, is formed on the semiconductor substrate. The floating gate (sometimes referred as the “charge storing layer”) of polysilicon, for example, is formed on the gate dielectric. The intergate dielectric layer (e.g., layers of SiO
2
, silicon nitride (“nitride”) and SiO
2
) is formed on the floating gate. The control gate of polysilicon, for example, is formed on the intergate dielectric layer. The floating gate formed on the SiO
2
gate dielectric defines a channel interposed between a source and a drain formed within the active region of the semiconductor substrate. The source and drain are formed by dopant impurities introduced into the semiconductor substrate.
Generally speaking, a FLASH memory cell is programmed by inducing hot electron injection from a portion of the semiconductor substrate, such as the channel section near the drain, to the floating gate. Electron injection introduces negative charge into the floating gate. The injection mechanism can be induced by grounding the source and a bulk portion of the semiconductor substrate and applying a relatively high positive voltage to the control gate to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain in order to generate “hot” (high energy) electrons. After sufficient negative charge accumulates in the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent “read” mode. The magnitude of the read current is used to determine whether or not a FLASH memory cell is programmed.
The act of discharging the floating gate of a FLASH memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source of the transistor (source erase or negative gate erase), or between the floating gate and the semiconductor substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source and a 0 V to the control gate and the semiconductor substrate while floating the drain of the respective FLASH memory cell.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, e.g., FLASH memory cells, having feature sizes as small as possible. Many present processes employ features, such as floating gates and interconnects, which have less than a 0.18 &mgr;m critical dimension. As feature sizes continue to decrease, the size of the resulting semiconductor device, as well as the interconnect between semiconductor devices, also decreases. Fabrication of smaller semiconductor devices allows more semiconductor devices to be placed on a single monolithic semiconductor substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area
As semiconductor device feature sizes decrease, the thicknesses of the SiO
2
layers in the intergate dielectric layer decrease as well. This decrease in SiO
2
layer thickness is driven in part by the demands of overall device scaling. As floating gate widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early semiconductor device scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. A maximum value of semiconductor device subthreshold current can be maintained while feature sizes shrink. Any or all of several quantities may be decreased by appropriate amounts including SiO
2
layer thickness, operating voltage, depletion width, and junction depth, for example.
As a result of the continuing decrease in feature size, SiO
2
layer thickness has been reduced so much that SiO
2
layers of the intergate dielectric layer are approaching thicknesses on the order of ten angstroms (Å) (1 nm). Unfortunately, thin SiO
2
layers may break down when subjected to an electric field, particularly SiO
2
layers less than 50 angstroms (Å) (10 nm) thick of the intergate dielectric layer. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such thin SiO
2
layers by a quantum mechanical tunneling effect. In this manner, a leakage current may undesirably form between the control gate and the floating gate, adversely affecting the operability of the device. For example, the leakage current increases exponentially for about a two-fold decrease in thickness of a SiO
2
layer. The exponential increase in the SiO
2
layer leakage current significantly affects the operation of semiconductor devices, particularly with regard to standby power, dissipation, reliability and lifetime.
Another disadvantage of thin SiO
2
layers is that some electrons may become entrapped within the SiO
2
layers by, e.g., dangling bonds. As a result, a net negative charge density may form in the SiO
2
layers of the intergate dielectric layer. As the trapped charge accumulates with time, the threshold voltage V
T
may shift from its design specification.
Still another disadvantage of thin SiO
2
layers is that a breakdown of the SiO
2
layers may also occur at even lower values of gate voltage, as a result of defects in the SiO
2
layers. Such defects are unfortunately prevalent in relatively thin SiO
2
layers. For example, a thin SiO
2
layer often contains pinholes and/or localized voids due to unevenness at which the SiO
2
layer grows on a less than perfect silicon lattice or is deposited on the nitride layer.
Additionally, the deposition of thin SiO
2
layers is more difficult to control due to inherent limitations of the deposition process. As devices are produced having layers with thicknesses on the order of a few monolayers, the thickness variation of these layers over a 200-mm or 300-mm silicon wafer is of substantial concern. A variation in thickness of only 1.0 angstrom (Å) (0.1 nm) could result in changes in the device operating conditions. For example, the electron or hole mobility or the device transconductance may be affected. Additionally, variations in layer thickness make it extremely difficult to maintain device tolerances. Further, the layer thicknesses not only vary within a wafer, but also vary from lot to lot which affects the manufacturing of wafers.
Therefore, there exists a strong need in the art for a dielectric layer which incorporates a high-K dielectric material which is formed with precise uniformity, thickness, abrupt atomic interfaces, etc., in order for semiconductor devices to be further scaled without reducing the data retention of the finished device. Additionally, the relatively high-K material increases the electric field in the intergate dielectric layer such that in an erase mode electrons in the charge storing layer will tunnel through the relatively low-K material of the SiO
2
gate dielectric.
SUMMARY OF THE INVENTION
One promising approach for maintaining the capacitance and thickness of the intergate dielectric layer may be to increase the permittivity of a layer(s) in order to “reduce” an electrical equivalent thickness of the layer(s) of

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