Precision frequency and phase synthesis with fewer...

Oscillators – Polyphase output

Reexamination Certificate

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C331S00100A, C331S016000, C331S057000, C375S376000, C327S156000

Reexamination Certificate

active

11250758

ABSTRACT:
A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The frequency synthesis circuit includes a sequence of adder-and-register units that select one of the VCO clock phases. An output multiplexer receives each of the selected clock phases, and selects among these clock phases in sequence; the output of the multiplexer is applied to a first toggle flip-flop that changes state in response to rising edge transitions at the output of the multiplexer. A second toggle flip-flop is clocked by the output of the first toggle flip-flop, itself toggling in response to rising edge transitions at the output of the first toggle flip-flop. One or more additional flip-flops can be similarly connected in sequence. The additional toggle flip-flop enables the VCO to be formed with fewer stages for a given frequency resolution, reducing noise and thus frequency error.

REFERENCES:
patent: 6329850 (2001-12-01), Mair et al.
patent: 6940937 (2005-09-01), Xiu et al.
patent: 2004/0008805 (2004-01-01), Xiu et al.
patent: 2005/0162552 (2005-07-01), Xiu et al.
BEST, Phase-Locked Loops: Design, Simulation, and Applications (McGraw-Hill, 1997), pp. 177-199.
Mair et al., “An Architecture of High-Performance Frequency and Phase Synthesis”, J. Solid State Circ., Vo. 35, No. 16 (IEEE, Jun. 2000), pp. 835-846.

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