Precision duty cycle phase lock loop

Details Precision duty cycle phase lock loop Precision duty cycle phase lock loop

1994-01-19

1996-03-19

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 23, 331 25, 324 7648, 329319, 329343, 327175, 327176, 327141, 327184, 327159, 327160, H03K 906

Patent

active

055006272

ABSTRACT:
An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

REFERENCES:
patent: 3579146 (1971-05-01), Paine
patent: 4134081 (1979-01-01), Pittaro
patent: 4144489 (1979-03-01), Ward et al.
patent: 4345211 (1982-08-01), Longworth
patent: 4475086 (1984-10-01), Allen
patent: 4713832 (1987-12-01), Hutson
patent: 5040197 (1991-08-01), Theobald
patent: 5095264 (1992-03-01), Hulsing, II

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