Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-11-06
2002-04-23
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S065000, C327S563000
Reexamination Certificate
active
06377085
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the biasing of a differential stage with active load, e.g., a transconductor. More particularly, the present invention relates to a precision biasing circuit in which the biasing circuit and the main circuit have almost identical biasing conditions.
The transconductance of a differential stage is controlled by its tail current. The tail current is in turn obtained by mirroring a reference current. In certain applications like controlled amplifiers or continuous-time filters that use transconductors, the reference current is used to adjust some of the characteristics of the transconductor (e.g. the transconductance). The accuracy of the replication of the reference current directly affects the performance of the transconductor, and so it is desirable to provide a circuit that very accurately replicates a reference current.
It would also be desirable to accurately mirror the reference current, especially for a low supply voltage.
Some applications, like programmable gain amplifiers, require a transconductor to be switched onto and off of a low input impedance stage, such as a cascode or a folded-cascode. In the latter case, the folded-cascode generally has a fully differential configuration and has its bias set by an output common-mode control loop. If there is a net DC output current from the transconductor, the common-mode control loop has to adjust the bias of the output stage every time the configuration changes by switching ON or OFF transconductors.
It would also be desirable to be able to accurately bias the active load of a differential stage in order to reduce the DC output currents of the differential stage connected to a folded-cascode current to be substantially zero.
FIG. 1
shows a conventional circuit
100
for biasing a differential stage. The circuit includes a differential stage
105
, a lower current mirror
110
, an upper current mirror
120
, a bias current source
125
, and first and second voltage sources
130
and
135
, representing the equivalent circuits of low impedance loads, e.g., as seen in
FIG. 5
below.
The differential stage
105
includes first through fourth differential transistors T
D1
, T
D2
, T
D3
, and T
D4
. The lower current mirror
110
includes first and second mirror transistors T
M1
and T
M2
. The upper current mirror
120
includes a third mirror transistor T
M3
and the third and fourth differential transistors T
D3
and T
D4
. The input transistors T
D1
and T
D2
are driven with respect to the common mode voltage V
COM
by the voltages v
id
/2 and −v
id
/2, respectively.
A tail current I
T
is obtained by mirroring a reference current I
BIAS
through the first and second mirror transistors T
M1
and T
M2
. Under ideal conditions, the tail current can be calculated as follows.
I
T
=2
n·I
BIAS
(1)
where n is determined by the ratio of the geometric features of first and second mirror transistors T
M1
and T
M2
as follows.
n
=
1
2
·
(
W
M1
L
M1
)
(
W
M2
L
M2
)
(
2
)
where W
M1
is the width of the first mirror transistor, L
M1
is the length of the first mirror transistor, W
M2
is the width of the second mirror transistor, and L
M2
is the length of the second mirror transistor.
The accuracy of the mirroring is affected by the usually different drain-source voltages of the first and second mirror transistors T
M1
and T
M2
.
One way to improve the current mirroring is to use cascode current mirrors, as shown in FIG.
2
. The circuit of
FIG. 2
includes a differential stage
105
, a cascode current mirror
210
, a bias current generator
125
, and first and second voltage sources
130
and
135
. The cascode current mirror
210
includes fourth, fifth, sixth, and seventh mirror transistors T
M4
, T
M5
, T
M6
, and T
M7
.
However, the cascode current mirrors have minimum voltage requirements that in many low-voltage deep-submicron circuits cannot be accommodated. As a result, the voltage at the node B must meet the following equality:
V
Bmin
=2·&Dgr;
V+V
TH
(3)
where V
TH
is the threshold voltage of the fourth, fifth, sixth, and seventh mirror transistors T
M4
, T
M5
, T
M6
, and T
M7
, and
Δ
V
=
I
T
K
(
W
M6
L
M6
)
(
4
)
where I
T
is the tail current, W
M6
is the width of the sixth mirror transistor T
M6
, L
M6
is the length of the sixth mirror transistor T
M6
, and K is a process-dependent parameter calculated as follows.
K
=
μ
·
C
ox
2
(
5
)
where &mgr; is the average mobility of the majority carriers in the channel, and C
ox
is the specific capacitance of the gate oxide.
For these equations, it is assumed that all of the bias transistors in one chain (T
M5
and T
M7
, T
M4
and T
M6
) are identical, and the body effect is neglected. Unfortunately, the minimum voltage on the B node V
Bmin
limits the input voltage range of the differential pair formed by the first and second differential transistors T
D1
and T
D2
.
A circuit using for bias a high swing cascode is shown in FIG.
3
. The circuit of
FIG. 3
includes a differential stage
105
, a high swing cascode current mirror
310
, first and second bias current sources
323
and
327
, and first and second voltage sources
130
and
135
. The high swing cascode current mirror
310
includes eighth through twelfth mirror transistors T
M8
to T
M12
.
The first and second bias current sources
323
and
327
do not necessarily supply the same current. Their output currents depend upon the relative sizes of the transistors T
M10
, T
M11
, and T
M12
.
The circuit shown in
FIG. 3
acts to lessen the minimum voltage at the node B to:
V
Bmin
=2·&Dgr;
V
(5)
Unfortunately, this may still not be low enough for certain bias conditions. In fact, many circuits require constant transconductance over process, temperature and power supply variations, which can easily cause a need for a 2:1 change in the bias current.
In each of the designs disclosed in
FIGS. 1
to
3
, the third and fourth differential transistors T
D3
and T
D4
of the differential pair
105
act as fixed current sources. In addition, the differential pair
105
itself also acts as a controlled current source. The output current of each branch of the differential stage T
D15
, T
D2
, T
D3
, and T
D4
is injected into an ideally zero input impedance stage, i.e., the first and second voltage sources
130
and
135
.
FIG. 4
shows and alternate configuration in which a transconductor is followed by a folded-cascode stage. The circuit of
FIG. 4
includes a differential stage
405
(voltage-to-current converter), a current mirror
110
, a bias current source
125
, and a folded-cascode
450
. The folded-cascode
450
includes first through fourth folded-cascode transistors T
FC1
to T
FC4
, a voltage amplifier
460
, and first and second load current sources
470
and
475
, and provides first and second output currents I
O1
and I
O2
. The differential stage
405
includes first and second differential transistors T
D1
and T
D2
.
In the circuit of
FIG. 4
, the loads of the differential stage are merged with the current sources of the folded-cascode and appear as the third and fourth folded-cascode transistors T
FC3
and T
FC4
. Their currents are controlled by a common-mode feedback loop including the first and second transistors T
FC1
and T
FC2
, and the voltage amplifier
460
.
FIG. 5
shows a folded-cascode transconductor that employs a separate input stage and folded-cascode for an NMOS differential stage. The circuit of
FIG. 5
includes a differential stage
105
, a lower current mirror
110
, an upper current mirror
120
, a bias current source
125
, and a folded-cascode
450
. The differential stage
105
provides first and second DC output currents I
DCO1
and I
DCO2
to the folded-cascode
450
.
A circuit similar to that of
FIG. 5
is shown, for example, in J- E. Kardontchik,
Introduction to the Design of Transconductor
-
Capacitor Filters,
Kluwer International Series in Engineering and Computer Sciences, 1992, which is
Cunningham Terry D.
Oki Semiconductor
Volentine & Francos, PLLC
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