Precise stopping of a high speed microprocessor clock

Details Precise stopping of a high speed microprocessor clock Precise stopping of a high speed microprocessor clock

1994-12-19

1997-09-16

Heckler, Thomas M.

G06F 104

Patent

active

056689837

ABSTRACT:
A method and means for selectively stopping the internal clock of a microprocessor on any of 16 phases using functional components which include: a clock multiplier circuit, that receives a clock signal input from an external oscillator or other appropriate source, and outputs the internal clock signal for the microprocessor; control logic circuitry for processing and inputting stop signals to the clock multiplier; and a clock special purpose register, which provides control signals to the control logic circuitry to determine when stopping of the internal clock signal should occur.

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"Method for Increasing the Accuracy of a Software Clock" R. Flyod et al., IBM Tech. Dis. Bulletin, vol. 29, No. 8 Jan. 1987, pp. 3374.

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