Precise digital generator producing clock signals

Oscillators – Ring oscillators

Reexamination Certificate

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Details

C331S00100A, C331S025000, C327S156000, C327S158000, C327S159000, C375S376000

Reexamination Certificate

active

06731178

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to phase-locked loop type clock-signal generators that produce a high-frequency clock signal from a low-frequency clock signal. Among these generators, the invention relates more specifically to those using a digital oscillator producing clock signals whose period is proportional to a binary number received by the oscillator.
BACKGROUND OF THE INVENTION
A prior art generator
10
of this kind, as illustrated in
FIG. 1
, has a comparator
12
and a digital oscillator
20
connected in series. An output OUT of the oscillator
20
is connected to an input of the comparator
12
. The generator
10
gives a high-frequency signal CKHF (with a period PHF) from a low-frequency reference signal CKBF (with a period PBF).
The comparator
12
has two inputs to which the high-frequency signal CKHF and the low-frequency reference signal CKBF are applied. The comparator
12
compares the period PHF of the high-frequency signal CKHF with a desired period PHF
0
. The desired period is, for example, a multiple of the period PBF. The comparator
12
produces a number NR of N
0
bits having the following characteristics: NR increases if PHF<PHF
0
, NR decreases if PHF>PHF
0
, otherwise NR is constant.
The comparator
12
produces the number NR, at N serial outputs, in the form of binary clock signals S(
1
) to S(N) representing the number NR. In the example of
FIGS. 1 and 2
, N=2
N0
and the signals S(
1
) to S(N) indicate the value of the number NR: S(NR+1)=1, and S(i)=0 for all values of i ranging from 1 to N and i≠NR+1. In another example, N=N
0
and the signals S(
1
) to S(N) correspond to N bits of the number NR.
The digital comparator
20
receives the binary signals S(
1
) to S(N) and produces the clock signal CKHF at the output OUT. It conventionally includes an odd number of inverters serially connected to form a chain. The period of the signal CKHF obtained depends primarily on the number of inverters and the propagation time of a 0 and a 1 in each inverter.
An exemplary oscillator
20
is shown in FIG.
2
. It has N cells C(
1
) to C(N) each comprising two inputs a, b and two outputs c, d. The N cells are series connected. The inputs a, b of the cells C(
1
) to C(N−1) are connected to the outputs c, d of the cells C(
2
) to C(N). The outputs c, d of the cell C(
1
) are connected together and form the output OUT of the oscillator
20
. The switches INTC(
1
) to INTC(N) are connected between the inputs a, b of each cell C(
1
) to C(N). The switches INTC(
1
) to INTC(N) are controlled by the signals S(
1
) to S(N). They are closed when the signals S(
1
) to S(N) are active.
The cells C(
2
) to C(N) are identical. Each cell has an even number NC of inverters series connected between the input and the output c and/or between the input b and the output d. Time periods TC
0
, TC
1
, possibly different from one another, are needed to propagate a 0 and a 1 respectively in all the elements of a cell C(
2
) to C(N), especially all the inverters.
The cell C(
1
) has a number NC′ of inverters series connected between the input a and the output b and/or the input c and the output d of the cell C(
1
). The number NC′ is an odd number to obtain the oscillations of the chain of inverters. Time periods TC
0
′, TC
1
′, possibly different from one another, are needed to propagate a 0 and a 1 respectively in all the elements of the cell C(
1
), especially all the inverters.
The clock-signal generator
10
operates as follows. The comparator gives a number NR
0
ranging from 0 to 2
N0
−1 in the form of the corresponding signals S(
1
) to S(N). In the example of
FIGS. 1 and 2
, S(NR
0
+1)=1 and S(i)=0 for i ranging from 1 to N, and i≠NR
0
+1. The switches INTC(
1
) to INTC(N) open and close as a function of the signals S(
1
) to S(N). The cells C(NR
0
+2) to C(N) are isolated and the cells C(
1
) to C(NR
0
+1) form a chain comprising an add total number of series connected inverters.
The propagation time of a 0 or a 1 between the cell C(NR
0
+1) and the cell C(
1
) depends on the propagation time in each cell. The oscillator
20
gives a signal CKHF at its output OUT. The period of this signal CKHF is equal to PHF=(TC
0
+TC
1
)*NR+(TC
0
′+TC
1
′) if the propagation time in the switch INTC(NR
0
+1) is overlooked. The period PHF is therefore proportional to the number NR given by the comparator.
If the period PHF of the clock signal CKHF obtained is smaller than the period desired PHF
0
, then the comparator increases the number NR to increase the number of cells in the chain, and thus increase the period of the signal CKHF. Conversely, if the period PHF of the signal CKHF obtained is greater than the desired value, then the number NR is reduced to reduce the period of the signal CKHF.
The number NR will thus vary gradually until the desired period PHF
0
is reached. The amplitude of the variations of NR is modulated as a function of the difference between the real period PHF of the signal CKHF and the desired period. Thus, when the generator
10
starts working, the period PHF is small, far smaller than PHF
0
and the comparator will vary the number NR substantially (+10, +50, +100 if necessary) to greatly increase the period PHF. Conversely, when PHF is close to PHF
0
, the number NR varies in smaller proportions (+1, −1) to obtain PHF=PHF
0
.
When NR increases or decreases by 1 respectively, a cell C is added or eliminated respectively in the chain. The minimum variation of the period in the oscillator is therefore equal to TC
0
+TC
1
, namely to the sum of the propagation times of a 0 and of a 1 in a cell C. The uncertainty over the period that defines the precision of the oscillator
20
is equal to P
0
=TC
0
+TC
1
.
The precision of the oscillator thus depends on the propagation times TC
0
, TC
1
in the cells C(
2
) to C(N), namely the number of inverters NC contained in these cells and the switching times t
0
, t
1
of these inverters. To improve the precision of the oscillator, it is possible to limit the number of inverters in a cell to NC=2 (the minimum) and/or to reduce the switching times of the inverters.
An inverter generally includes a P-type transistor and an N-type transistor that are series connected. The source of the P-type transistor is connected to a supply VDD and the source of the N-type transistor is connected to ground of the circuit. The gates of the transistors are connected together and form the input of the inverter. The drains of the transistors are connected together and form the output of the inverter.
The switching time of an inverter of this kind is proportional to L
2
, with L being the length of the gate of the transistors. To reduce the switching times, it is necessary to reduce the gate length L of the transistors. However, the gate length L of the transistors cannot be reduced beyond a minimum length Lmin which depends on the technology chosen to make the integrated circuit. Beyond this limit Lmin, it is no longer possible to make the transistors. The switching time t
0
, t
1
of the inverters therefore cannot be reduced beyond the minimum value t0 min, t1 min.
Consequently, the propagation times TC
0
, TC
1
in the cells C(
2
) to C(N) are themselves limited by these minimum values. This approach is therefore not sufficient especially if it is required that the uncertainty with regard to the period of the signal CKHF obtained should be very low, for example 1%. The term uncertainty must be understood to mean the maximum variation in period of the signal CKHF when the number NR varies by 1.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the invention is to provide an oscillator that is different and, in particular, precise, and to provide a clock-signal generator that uses this oscillator. The generator of the invention provides clock signals CKHF with a frequency of about 50 M

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