Precise delay line circuit with predetermined reset time limit

Details Precise delay line circuit with predetermined reset time limit Precise delay line circuit with predetermined reset time limit

1995-12-06

1998-09-01

Cunnigham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327143, 327198, 327271, H03H 1126

Patent

active

058015680

ABSTRACT:
A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.

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patent: 5192886 (1993-03-01), Wetlaufer
patent: 5309037 (1994-05-01), Curley et al.
patent: 5367490 (1994-11-01), Akimoto et al.

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