Precharged power-down biasing circuit

Details Precharged power-down biasing circuit Precharged power-down biasing circuit

2007-04-17

2007-04-17

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

10854635

ABSTRACT:
A power-down biasing circuit including a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first capacitor connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches. Each current mirror has a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage; a second capacitor connected between the gate of the first PMOS transistor and the supply voltage; and at least two PMOS transistors are connected as a current multiplier to the output switches. A second NMOS transistor may be added in parallel with the current source, with a gate that is driven by the same signal that drives the first switch. A third NMOS transistor may be added in parallel with the current multiplier, with a gate that is driven by an inverse of the signal that drives the first switch.

REFERENCES:
patent: 5654981 (1997-08-01), Mahant-Shetti et al.
patent: 6107789 (2000-08-01), Fryer et al.
patent: 6281730 (2001-08-01), Vu
patent: 6509855 (2003-01-01), Cable
patent: 6525598 (2003-02-01), Croman
patent: 6617915 (2003-09-01), Rajan
patent: 6680605 (2004-01-01), Chen et al.

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